|Branch timing and interrupts
|Page 1 of 1|
|Author:||zeroone [ Fri Jul 24, 2015 1:47 pm ]|
|Post subject:||Branch timing and interrupts|
From http://nesdev.com/6502_cpu.txt :
Relative addressing (BCC, BCS, BNE, BEQ, BPL, BMI, BVC, BVS)
# address R/W description
--- --------- --- ---------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch operand, increment PC
3 PC R Fetch opcode of next instruction,
If branch is taken, add operand to PCL.
Otherwise increment PC.
4+ PC* R Fetch opcode of next instruction.
Fix PCH. If it did not change, increment PC.
5! PC R Fetch opcode of next instruction,
Notes: The opcode fetch of the next instruction is included to
this diagram for illustration purposes. When determining
real execution times, remember to subtract the last
* The high byte of Program Counter (PCH) may be invalid
at this time, i.e. it may be smaller or bigger by $100.
+ If branch is taken, this cycle will be executed.
! If branch occurs to different page, this cycle will be
Does "Fetch opcode of next instruction" appear in those cycles due to pipelining? Meaning, does this timing actually reflect part of the next instruction?
Also, do those possible cycles cause interrupts to be delayed immediately after a branch? Or, is that an effect of something else?
Edit: This link answered all my questions. Thanks anyway.
|Page 1 of 1||All times are UTC - 7 hours|
|Powered by phpBB® Forum Software © phpBB Group