|NES Dev WIKI - few bugs, update request
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|Author:||krzysiobal [ Sun Dec 13, 2015 6:38 pm ]|
|Post subject:||NES Dev WIKI - few bugs, update request|
Please add it in free time as it might be useful for developers:
1. Timings from CPU and PPU cycles (UA6527P, UA6538):
There is some misunderstanding:
ALE (Address Latch Enable) goes high at the beginning of a PPU VRAM access and is used to latch the lower 8 bits of the PPU's address bus; see the PPU address bus section of PPU rendering. It stays high for one PPU cycle.
No it doesnt, the real ALE timing is shown on my picure. Also, there shouldnt be 'VRAM' but 'VRAM/CHR-ROM/CHR-RAM'
2. I investigated the state of CPU & PPU pins on reset.
When CPU is held on reset (PIN3 = LOW), the whole bus (A0-A15, D0-D7, M2, OUT0-2 (PIN39,38,37), PORT2_!OE (PIN 36), PORT1_!OE (PIN35)) is in high impedance state.
When PPU is held on reset (PIN22 = LOW):
The PPU-side bus (ALE,AD0-AD7,A8-A13,!RD,!WE) is NOT in high impedance state.
ALE is LOW, AD0-AD7, A8-A13 is LOW, !RD,!WE is high
The CPU-side bus (D0-D7: pins 2-9) is in high impedance state ONLY when !CE (pin 13) is high, otherwise they are all LOW! For example - reading PPUSTATUS when PPU is held in reset will return $00 all the time.
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