It is currently Wed Oct 18, 2017 11:45 am

All times are UTC - 7 hours





Post new topic Reply to topic  [ 4 posts ] 
Author Message
 Post subject: MMC5 irq hardware timing
PostPosted: Fri Apr 28, 2006 5:04 pm 
Offline

Joined: Thu Oct 27, 2005 1:44 pm
Posts: 449
Location: CA
I am trying to figure out when the scanline irq is generated relative to the ppu memory accesses. Most docs say it comes when the scanline starts being rendered which is good for emulators but not accurate enough for hardware. The two options I could see are:

1. New scanline is found when there are 3 sequential name table reads, IRQ generated at that time. IRQ comes after the first 2 tiles are prefetched on the previous scanline. Seems to match the clock cycle count done by blargg.

2. New scanline starts when the first tile is prefetched, right after the sprites are read. IRQ starts then so no tiles are missed. Makes more sense but doesnt match the clock counts?

From what I have been able to tell from emulator source is they do #2, but also dont bother with emulating the hardware exactly because it isnt needed. Best would be to know which ppu memory access the irq coincides with.


Top
 Profile  
 
 Post subject:
PostPosted: Sat Apr 29, 2006 12:35 am 
Offline
User avatar

Joined: Fri Nov 12, 2004 2:49 pm
Posts: 7229
Location: Chexbres, VD, Switzerland
The MMC5 IRQs are triggered right at the end of HBlank. Check the firefly demo to test this.

_________________
Life is complex: it has both real and imaginary components.


Top
 Profile  
 
 Post subject:
PostPosted: Sat Apr 29, 2006 12:28 pm 
Offline

Joined: Thu Oct 27, 2005 1:44 pm
Posts: 449
Location: CA
And HBlank time is entirely used up by the sprite fetching, so the IRQ is triggered when the first background tile is being fetched? Usually the two name table reads (memory fetches 169-170) are labelled as the end of the scanline so I think thats where my confusion comes in...


Top
 Profile  
 
 Post subject:
PostPosted: Sat Apr 29, 2006 12:40 pm 
Offline
User avatar

Joined: Sun Sep 19, 2004 10:59 pm
Posts: 1389
No - the MMC5 generates its IRQs exactly at "cycle 0" on each scanline - that is, when it starts to fetch the 3rd tile.

It is not known exactly how the MMC5 detects this, though the chip does stay more or less perfectly synchronized with the PPU via its memory accesses.

_________________
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.


Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 4 posts ] 

All times are UTC - 7 hours


Who is online

Users browsing this forum: adam_smasher and 5 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group