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PostPosted: Fri Sep 09, 2016 7:06 am 
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lidnariq wrote:
To make sure I understand: DIP switch bank 1 is the bank for the master CPU, and DIP switch bank 2 is for the slave CPU?

Yes.
lidnariq wrote:
So theoretically, whatever is in the master CPU shouldn't be able to care about what's going on in bank 2, and vice versa?

That is my understanding, as I didn't see Balloon Fight resetting or any other weird behaviors. I was asking the same question, though, as I'm not sure. :)
lidnariq wrote:
What's confusing me is the bit where your picture in the album ( https://imgur.com/KlZBirb ) shows DIP switches 1-7 as OFF, but the value on-screen ( https://imgur.com/V45mBgb ) shows all DIP switches as ON. Hence asking about temporal order. And also asking if anything's seemed suspicious when games are run on the master side of this specific board.

I may have gotten one of the pictures out of sequence, although I do remember the reported dip values seeming odd on 1 or 2 occasions. I'll try to re-test late tonight and clarify the dip settings.
lidnariq wrote:
As far as we know, the 2A04 is "just" a jumper between pin 20 and pin 38, causing the shared RAM to always be granted to the "slave" CPU. (For example, Vs. SMB relies on having access to that extra 2 KiB of RAM, but its documentation also says several other games—but not all—are sufficiently equivalent to the 2A04)

So does that mean it isn't a CPU at all, and literally just a DIP package jumping pins 20 and 38?
lidnariq wrote:
If you're willing to sit down with a multimeter and see if that is true, that would be helpful! (And maybe see if any other pins are shorted, too?)

That is absolutely something I'm willing to do. I've got a decent meter, and I can check those things easily for you.
lidnariq wrote:
Well, thefox wrote this test that detects the not-missing PPU pixel on the 2C03. I guess it would be nice to verify the same is true on the 2C04... except that it's no longer accessible :(

I'm not sure I'm following, unless you meant the 2 palette colors that are different on that PPU.
lidnariq wrote:
If we do write some tests, do you have any of the Vs. System daughtercards that add a more complicated memory manager hardware (e.g. 108 or VRC or MMC1)? And/or have you modified your mainboard to support Vs. Gumshoe?

OH YEAH. I got you covered there, I think I have almost all of them, except for 1, and a friend has that one. I also have almost all of the varieties of PPUs, if that helps anyone. FYI, the auto detect of PPUs didn't seem to work for the RC2C03B PPU that I was using. I always had to press right once to select that PPU. Edit: My boards do not appear to have the memory mod on either one of them. I wouldn't mind doing it on one of the boards if it helps anyone here out.
lidnariq wrote:
[From other thread] Oh, you have the UNROM daughterboard. Could you try tepples's test suite? A lot of the tests won't be relevant on a SD CRT, or sensible on a RGB PPU, but a few (like the "overscan" test) would be nice to have data from.

Yes, that should be no problem. In fact, if we want to know what happens on an SD TV, I have a NES-pulled PPU that we could drop in, and I could run the composite line to a nearby Sony monitor that I have...

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PostPosted: Fri Sep 09, 2016 8:00 am 
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lupin3rd wrote:
lidnariq wrote:
Well, thefox wrote this test that detects the not-missing PPU pixel on the 2C03. I guess it would be nice to verify the same is true on the 2C04... except that it's no longer accessible :(

I'm not sure I'm following, unless you meant the 2 palette colors that are different on that PPU.

The NTSC NES PPU (2C02) takes a 945/44 = 21.4773 MHz clock input and produces a video signal that's 1364 master clocks (341 pixels) wide by 262 scanlines tall, including blanking, for a total of 357368 master clocks per field. But when rendering is enabled, every other field is shorter by four master clocks (one pixel) because one pixel is removed from the horizontal blanking between the pre-render line and the first picture line. This is done to align the color subcarrier from one field to the next, producing a 2-frame cycle that TVs may handle better than a 3-frame cycle. Thus the average field is (357368 + 357364) = 357366 master clocks long, for a field rate of 945/44*1000000/357366 = 60.0988 Hz.

But because the RGB PPU (2C03, 2C04, 2C05) doesn't have a color subcarrier, it doesn't need to drop the extra dot. Thus every field is 357368 master clocks long, for a field rate of 945/44*1000000/357366 = 60.0985 Hz.

The difference between 357366 and 357368 master clocks is one CPU cycle (12 master clocks) every six fields. By waiting for this difference to accumulate over the course of several fields, such as while a copyright notice is displayed, a program can distinguish an RGB PPU from an NTSC PPU. A homebrew game might use this information to A. replace $2D gray with $00 gray or B. use (slower, less smooth) palette modifications instead of color emphasis.

lupin3rd wrote:
FYI, the auto detect of PPUs didn't seem to work for the RC2C03B PPU that I was using. I always had to press right once to select that PPU.

How does the autodetect work? Is there really a difference between 2C03 and 2C04 other than the palette ROM inside the PPU? I know 2C05 has swapped $2000 and $2001 and a signature on $2002, but are 2C05 PPUs common enough in the wild that Vs. homebrew ought to support them?


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PostPosted: Fri Sep 09, 2016 1:41 pm 
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lupin3rd wrote:
OH YEAH. I got you covered there, I think I have almost all of [the daughterboards], except for 1, and a friend has that one.
There are a few lot of questions about the daughterboards, actually..
1- For the VRC-using one (for Vs. Goonies and Vs. Gradius), could you find out what (if anything) VRC pins 15 and 17 are connected to?
(Maybe also verify the pins with question marks next to them on http://wiki.nesdev.com/w/index.php/VRC1_pinout ? )
2- Do you have any of the 108-using ones with the additional copy protection ICs? (126 for "TKO Boxing", 127 for "Atari RBI Baseball", and ??? for "Super Xevious")
If so, I'd like to write a test that will shed some more light on what they're doing. All we have right now is Nocash's notes.
2b- Actually, I'd like to run some arbitrary code on a 108 to see if we can figure out more specifics about a bug that Naruko found.
3- If you have the SUNSOFT-3 using Vs. Platoon, we don't have a pinout for that chip. It'd be nice to get one.

4- Lots of the daughterboards have extra hardware (DIP switches, other ICs) on them but the manuals don't say anything about them. It'd be nice to know what's going on with them...
(For example: the VRC-using 302163 has a 74LS00 and a 74LS32. Vs. Platoon has a 74LS04 and four switches. RBI has a 74LS139 and two 74LS00s. What are all these things doing?)

Quote:
I also have almost all of the varieties of PPUs, if that helps anyone.
there is a question about the 2C05-02: wiki talk. It'll need another test written.

Quote:
FYI, the auto detect of PPUs didn't seem to work for the RC2C03B PPU that I was using. I always had to press right once to select that PPU.
The autodetection can only detect the 2C05. I don't think there's any way for the software to detect which of the other five PPUs it's running on.

tepples wrote:
are 2C05 PPUs common enough in the wild that Vs. homebrew ought to support them?
As far as I know, the 2C05s each matched to one game and only one game. I don't think they're meaningfully differently rare than each of the 2C04 PPUs...

For a characterization test it was easy enough to add the logic to detect 2C05s and automatically switch $2000 and $2001 as appropriate.

And for "ordinary" use it's utterly trivial to change two assemble-time constants to support them, and that's easier than reworking all the palette handlers for the 2C04s...

lupin3rd wrote:
My boards do not appear to have the memory mod on either one of them. I wouldn't mind doing it on one of the boards if it helps anyone here out.
Nah, no need. It only would have been useful if we'd had a set of tests we wanted to put together and you hadn't had any daughterboards.

lupin3rd wrote:
Yes, that should be no problem. In fact, if we want to know what happens on an SD TV, I have a NES-pulled PPU that we could drop in, and I could run the composite line to a nearby Sony monitor that I have...
Tepples has been developing the 240p test suite against a SD CRT TV, so most of that behavior is known. It's mostly just figuring out how the RGB PPUs differ.


Here's a list of a few other things that might be interesting to check, but will need tests written or found:
• Do writes to $2003 corrupt the sprite table (like the 2C02)?
• Does leaving the value in $2003 at a value of 8 or higher corrupt the sprite table (like the 2C02)?
• Is it possible to read back the sprite table via $2004 (like the 2C02E and 2C02G, unlike the 2C02, 2C02A, 2C02C)?
• Is palette readback completely missing? (previous test implies yes)


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PostPosted: Fri Sep 09, 2016 2:21 pm 
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Okay, so I have the following daughterboards:

  • Gradius (Goonies) board
  • Atari RBI Baseball
  • VS Castlevania

I think that's all I have currently. So there are definitely more that I don't have, but I wasn't making the distinction between the different types of copy protection, etc. And I also have access to a VS Dr. Mario board. I'm actively working on fleshing out my collection of these items, so this list may be subject to change.

I can definitely figure out where some of those pins are going.
lidnariq wrote:
there is a question about the 2C05-02: wiki talk. It'll need another test written.

Is that the Gumshoe PPU? If so, I have it, but I have not verified that it works since i don't have a gun setup yet. I may be able to help there. If it's NOT the Gumshoe PPU, I don't have it.
lidnariq wrote:
The autodetection can only detect the 2C05. I don't think there's any way for the software to detect which of the other five PPUs it's running on.

Okay, since it said "auto detecting PPU" and came up with nice colors, I assumed it worked -- but I guess I was using an SMB PPU 2C04-0001, which is probably the default for the test suite. Since you can't read palette data back, and there is no difference with registers, that makes sense.

I believe I have the following PPUs (at your disposal, if you want testing done with any of them):

  • 2C02G (or whatever a standard USA NES-001 used)
  • RP2C04-0001 (Works)
  • RP2C04-0002 (Works)
  • RP2C04-0003 (Works)
  • RP2C04-0004 (Works)
  • RC2C03B (Works, but I have to be careful with it, because it has about 8 leg-repairs on it; chip was corroded when I got it)
  • RC2C05-03 (Not sure if working)

I have one NES that is in a desoldered state, where the RAM, CPU, PPU, and CIC chips have all been removed. I was planning on socketing all of it, so that I could begin some of my own experiments. Doubtful it would help anyone, but if any weird Frankenstein testing is needed, that too is available.

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PostPosted: Fri Sep 09, 2016 2:39 pm 
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lupin3rd wrote:
Atari RBI Baseball
Oo. Ok.

We know the pinout of the 108 ... as well as the CPU and PPU and ROMs.

Certainly right now I could write something that would just dump more bits of the stream that nocash wrote about, but to do anything more clever I'd need to know how the other ICs are attached.

lupin3rd wrote:
Is [the 2C05-02] the Gumshoe PPU? If so, I have it, but I have not verified that it works since i don't have a gun setup yet. I may be able to help there. If it's NOT the Gumshoe PPU, I don't have it.
No, it's the Mighty Bomb Jack PPU. Gumshoe is the 2C05-03...

Quote:
I believe I have the following PPUs (at your disposal, if you want testing done with any of them):
I don't think there's any tests we'll need to try the other PPUs for, other than the two you have in your red tent right now.


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PostPosted: Fri Sep 09, 2016 2:44 pm 
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lidnariq wrote:
... but to do anything more clever I'd need to know how the other ICs are attached.

Okay, I can do some tracing on the Atari RBI Baseball daughterboard to see where the pins in question are going.

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PostPosted: Sat Sep 10, 2016 12:04 am 
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lidnariq wrote:
1- For the VRC-using one (for Vs. Goonies and Vs. Gradius), could you find out what (if anything) VRC pins 15 and 17 are connected to?

Pin 15, is a solder pad that is not connected by default, but if it were bridged, it would be circling back to pin 20 on the VRC. Pin 17: No connection.
lidnariq wrote:
(Maybe also verify the pins with question marks next to them on http://wiki.nesdev.com/w/index.php/VRC1_pinout ? )

VRC question mark pins (as found on the Gradius daughterboard labeled - MDS-EXP1-01 R-7HB KONAMI 302163):

  • Pin 25: PPU A12 (Pin 26)
  • Pin 24: No connection
  • Pin 23: No connection
  • Pin 21: CPU R/W (RP2A03 Pin 34)
  • Pin 19: PPU A13 (Pin 25)
  • Pin 18: PPU /RD (Pin 24)
  • Pin 17: No connection
  • Pin 16: LS32 (U1) 3Y (Pin 8)

lidnariq wrote:
2b- Actually, I'd like to run some arbitrary code on a 108 to see if we can figure out more specifics about a bug that Naruko found.

Let me know when the test is written, and I can give you the output. :)

lidnariq wrote:
4- Lots of the daughterboards have extra hardware (DIP switches, other ICs) on them but the manuals don't say anything about them. It'd be nice to know what's going on with them...
(For example: the VRC-using 302163 has a 74LS00 and a 74LS32... snip... RBI has a 74LS139 and two 74LS00s. What are all these things doing?)

VRC-using 302163:

74LS00 (U2) - Quad Input NAND Gate
  • Pin 7 (Gnd): GND
  • Pin 8 (1Y): 74LS32 (U1) Pin 1 (1A) and Pin 9 (3A)
  • Pin 9 (1A): CPU A15 (Pin 19)
  • Pin 10 (1B): CPU M2 (Pin 31)
  • Pin 14 (Vcc): 5V

74LS32 (U1) - Quad Input OR Gate
  • Pin 1 (1A): Connected to Pin 9 (Also 74LS00 1Y Pin 8)
  • Pin 2 (1B): GND
  • Pin 3 (1Y): Connected to 2A (Pin 4)
  • Pin 4 (2A): Connected to 1Y (Pin 3)
  • Pin 5 (2B): GND
  • Pin 6 (2Y): Connected to 4A (Pin 12)
  • Pin 7 (Gnd): GND
  • Pin 8 (3Y): VRC (Pin 16)
  • Pin 9 (3A): Connected to Pin 1 (Also 74LS00 1Y Pin 8)
  • Pin 10 (3B): Bridged to Pin 11
  • Pin 11 (4Y): Bridged to Pin 10
  • Pin 12 (4A): Connected to 2Y (Pin 6)
  • Pin 13 (4B): GND
  • Pin 14 (Vcc): 5V

74LS373 (U5) - Octal D Type Transparent Latches and Edge Triggered Flip Flops
  • Pin 1 (/OC): GND
  • Pin 2 (1Q): CHR A7 (Pin 3)
  • Pin 3 (1D): CHR Q7 (Pin 19)
  • Pin 4 (2D): CHR Q5 (Pin 17)
  • Pin 5 (2Q): CHR A5 (Pin 5)
  • Pin 6 (3Q): CHR A3 (Pin 7)
  • Pin 7 (3D): CHR Q3 (Pin 15)
  • Pin 8 (4D): CHR Q1 (Pin 12)
  • Pin 9 (4Q): CHR A1 (Pin 9)
  • Pin 10 (Gnd): GND
  • Pin 11 (C): PPU ALE (Pin 39)
  • Pin 12 (5Q): CHR A0 (Pin 10)
  • Pin 13 (5D): PPU AD0 (Pin 38)
  • Pin 14 (6D): PPU AD2 (Pin 36)
  • Pin 15 (6Q): CHR A2 (Pin 8)
  • Pin 16 (7Q): CHR A4 (Pin 6)
  • Pin 17 (7D): PPU AD4 (Pin 34) (and CHR Q4 Pin 16)
  • Pin 18 (8D): PPU AD6 (Pin 32) (and CHR Q6 Pin 18)
  • Pin 19 (8Q): CHR Q7 (Pin 4)
  • Pin 20 (Vcc): 5V

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PostPosted: Sat Sep 10, 2016 12:35 pm 
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lupin3rd wrote:
VRC-using 302163:
Pin 15, is a solder pad that is not connected by default, but if it were bridged, it would be circling back to pin 20 on the VRC.
So that solder pad would make it possible use a 28-pin 128 KiB CHR ROM ... which is almost useless because no programmable 28-pin 128 KiB ROMs were ever made. But I guess you could desolder the Mask ROM from any of the famicom VRC-using games.

Quote:
74LS00 (U2) - Quad Input NAND Gate
And the other three NAND gates aren't used? Ok, so this is generating /ROMSEL from M2 and A15, like the NES mainboard. Because the VRC needs that inverted signal...

Quote:
74LS32 (U1) - Quad Input OR Gate
This is so much weirder than I would have thought. It's using the four OR gates as a pulse-narrow-er, so that the signal rises the moment M2 or A15 falls, but takes a while to fall after both M2 and A15 are high.

Quote:
74LS373 (U5) - Octal D Type Transparent Latches and Edge Triggered Flip Flops
... Right, of course the daughterboard needs its own latch for the PPU. It doesn't plug into the CHR ROM sockets on the mainboard, so it has to re-derive that.


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PostPosted: Sat Sep 10, 2016 4:29 pm 
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Let me know when you're ready to crack the mysteries of the VS RBI Baseball daughterboard.

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PostPosted: Sat Sep 10, 2016 4:50 pm 
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I think I'm satisfied with the VRC now, so it'd be lovely if you could determine the connectivity of the 74'139, the two 74'00s, the DIP switches, the 127, and ... what are those two diodes (1S1588) doing?

I'm idly curious what's going on with the PRG2 socket (mostly, where does it differ from PRG1? I suppose it might be designed to take two 64 KiB 'PROMs for ROM, and part of the '139 and the DIP switches might let you control whether one socket, the other, or both sockets are available to the game?)

No need to check the 74'373, we can be confident it's identical in function (if not the exact same pinout) as when it's on the VRC board.

I've started working on something that will hopefully be able to shed light on Naruko's bug ... would you rather have to program more ROMs, or wait for me to get everything into a single image?


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PostPosted: Sun Sep 11, 2016 12:11 am 
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lidnariq wrote:
I think I'm satisfied with the VRC now, so it'd be lovely if you could determine the connectivity of the 74'139, the two 74'00s, the DIP switches, the 127, and ... what are those two diodes (1S1588) doing?

Okay, I'll report back after I've mapped those things out. May take me an extra day or two, as I'm covered up all day tomorrow.

lidnariq wrote:
I'm idly curious what's going on with the PRG2 socket (mostly, where does it differ from PRG1? I suppose it might be designed to take two 64 KiB 'PROMs for ROM, and part of the '139 and the DIP switches might let you control whether one socket, the other, or both sockets are available to the game?)

That's my understanding, too, that an additional PRG ROM could be provided, but I'm not aware of any games that actually used that option...

lidnariq wrote:
I've started working on something that will hopefully be able to shed light on Naruko's bug ... would you rather have to program more ROMs, or wait for me to get everything into a single image?

I don't mind burning additional ROMs. I like helping out around here, so if I can get info quicker to you by running tests as you make them, that's what I'll do. Plus, it may be helpful for me to run the tests as they are developed, because we might have some bug fixes/QA discoveries or additional test ideas that pop up as we move along. :)

Follow-up on Dipswitches:

  • When all dips are set in the OFF position, and running the test suite on the slave side, the system reports: 80 00
  • When all dips are set in the ON position, and running the test suite on the slave side, the system reports: 98 FC

I will run the test on the master side tomorrow to see if the dips report differently.

Just wanted to take a second to thank you guys for being so helpful with all my questions. Not used to that treatment online, and I'm awestruck with how much work you guys have put in to keep the wiki updated and accurate.

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PostPosted: Tue Sep 13, 2016 1:07 am 
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lidnariq wrote:
I think I'm satisfied with the VRC now, so it'd be lovely if you could determine the connectivity of the 74'139...

74LS139 Dual 2-Line to 4-Line Decoder / Demultiplexer
Pin 1 /1Enable: Pin 11
Pin 2 1Da: PRG1 and PRG2 A12 (Pin 2)
Pin 3 1Db: CPU A13 (Pin 17)
Pin 4 /1Y0: NC
Pin 5 /1Y1: (127) Pin 20
Pin 6 /1Y2: NC
Pin 7 /1Y3: NC
Pin 8 GND: GND
Pin 9 /2Y3: NC
Pin 10 /2Y2: NC
Pin 11 /2Y1: Pin 1
Pin 12 /2Y0: NC
Pin 13 2Db: 74HC00 Y3 (Pin 8)
Pin 14 2Da: NC
Pin 15 /2Enable: (127) Pin 22
Pin 16 VCC: +5V

lidnariq wrote:
... the two 74'00s ...

There is a 74HC00 and a 74HC08...

74HC00P Quadruple 2-input Positive NAND Gate
Pin 1 A1: GND
Pin 2 B1: GND
Pin 3 Y1: NC
Pin 4 A2: NC
Pin 5 B2: 74LS139 2Db (13) + CPU A15 (19)
Pin 6 Y2: 108 (10)
Pin 7 GND: GND
Pin 8 Y3: 127 (22) + 74LS139 /2E (Pin 15)
Pin 9 A3: CPU (31) Bridged to Pin 10
Pin 10 B3: CPU (31) Bridged to Pin 9
Pin 11 Y4: PRG1 (20)
Pin 12 A4: PRG2 (20) Bridged to Pin 13
Pin 13 B4: PRG2 (20) Bridged to Pin 12
Pin 14 Vcc: +5V

M74HC08P Quadruple 2-input Positive AND Gate
Pin 1 A1: GND
Pin 2 B1: GND
Pin 3 Y1:
Pin 4 A2: GND
Pin 5 B2: GND
Pin 6 Y2:
Pin 7 GND: GND
Pin 8 Y3: 108 (Pin 7)
Pin 9 B3: Bridged 10 -> Dip3
Pin 10 A3: Bridged 9 -> Dip3
Pin 11 Y4: PRG1 (Pin 1)
Pin 12 B4: Bridged 13
Pin 13 A4: Bridged 12
Pin 14 Vcc: +5V

lidnariq wrote:
... the DIP switches ...

Dip 1: 108 (Pin 28) - when closed - connects to 74HC08 (Pins 12+13)
Dip 2: PRG1 + PRG2 (Pins 27) - when closed - connects to same PRG1+PRG2 (Pins 27)
Dip 3: 108 (Pin 12) - when closed - connects to 74HC08 (Pins 9+10)
Dip 4: 108 (Pin 13) - when closed - connects to CHA (Pin 27)

lidnariq wrote:
... the 127 ...

Custom 1 (127):

Pin 1: CPU (Pin 40)
Pin 2: NC
Pin 3: PRG2 A7 (Pin 3) and PRG1 (Pin 3)
Pin 4: PRG2 A6 (Pin 4) and PRG1 (Pin 4)
Pin 5: PRG2 A5 (Pin 5) and PRG1 (Pin 5)
Pin 6: PRG2 A4 (Pin 6) and PRG1 (Pin 6)
Pin 7: PRG2 A3 (Pin 7) and PRG1 (Pin 7)
Pin 8: PRG2 A2 (Pin 8) and PRG1 (Pin 8)
Pin 9: PRG2 A1 (Pin 9) and PRG1 (Pin 9)
Pin 10: PRG2 A0 (Pin 10) and PRG1 (Pin 10)
Pin 11: PRG2 D0 (Pin 11) and PRG1 (Pin 11)
Pin 12: PRG2 D1 (Pin 12) and PRG1 (Pin 12)
Pin 13: PRG2 D2 (Pin 13) and PRG1 (Pin 13)
Pin 14: GND
Pin 15: PRG2 D3 (Pin 15) and PRG1 (Pin 15)
Pin 16: PRG2 D4 (Pin 16) and PRG1 (Pin 16)
Pin 17: PRG2 D5 (Pin 17) and PRG1 (Pin 17)
Pin 18: PRG2 D6 (Pin 18) and PRG1 (Pin 18)
Pin 19: PRG2 D7 (Pin 19) and PRG1 (Pin 19)
Pin 20 74LS139 /1Y1 (Pin 5)
Pin 21: PRG2 A10 (Pin 21) and PRG1 (Pin 21)
Pin 22: 74LS139 /2Enable (Pin 15)
Pin 23: NC?
Pin 24: PRG2 A9 (Pin 24) and PRG1 (Pin 24)
Pin 25: PRG2 A8 (Pin 25) and PRG1 (Pin 25)
Pin 26: NC?
Pin 27: NC?
Pin 28: +5V

lidnariq wrote:
... and ... what are those two diodes (1S1588) doing?

PPU A10 (Pin 28)
PPU A9 (Pin 29) -> D1 -> (CHR-ROM) Pin 28
PPU A8 (Pin 30) -> D2 -> (and also CHR-ROM Pin 25) -> 1A (CHR-ROM) Pin 28

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PostPosted: Tue Sep 13, 2016 1:20 am 
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Oh, I also re-ran the Characterization test again, but on the master side this time.

With all dips OFF - System reported DIPSWITCHES: 00 00
With all dips ON - System reported DIPSWITCHES: 18 FC

Just thought I'd follow up and mention that. :)

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PostPosted: Tue Sep 13, 2016 12:33 pm 
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lupin3rd wrote:
74LS139 Dual 2-Line to 4-Line Decoder / Demultiplexer
Decoder 2: detect when A15 is low and M2 is high.
Decoder 1: Detect when A15 low, M2 high, A12 high, A13 low.

... interesting, A14 isn't involved. There should be bus conflicts if the game ever read from the pointless (redundant) region at addresses $1000-$1FFF.

Quote:
74HC00P Quadruple 2-input Positive NAND Gate
NAND1: unused
NAND2: invert CPU A15 (for N108 in lieu of /ROMSEL)
NAND3: invert M2 (for '139)
NAND4: invert PRG2/CE into PRG1/CE

Does nothing ever drive PRG2/CE ? ... is it connected to N108 pin 23 (PRG A16) ?
Quote:
M74HC08P Quadruple 2-input Positive AND Gate
AND1, AND2: unused
AND3: buffers signal on far side of DIP3 to ... N108 ground? Are you sure it's N108 pin 7? By context it should be CHA pin 1.
AND4: buffers signal on far side of DIP1 to PRG1/2 A15

DIP1: shorted: 64 KiB PRG (relay N108 PRG A15). open: 32 KiB PRG (drive ROM PRG A15 with value floating on 74HC input??)
DIP2: if it only connects to itself ... who knows. By context, it looks like it was intended to control PRG A14 in the same way as the other DIP switches.
DIP3: shorted: should allow for 64 KiB CHR (relay N108 CHR A15). open: 32 KiB CHR (drive ROM CHA A15 with value floating on 74HC input??)
DIP4: shorted: allow for 32 KiB CHR (connect N108 CHR A14). open: 16 KiB CHR (ROM CHA A14 float)

Quote:
Custom 1 (127)
Oh, that's fascinating. That's pretending to be a ROM.

It's using /M2 as "ROM"/CE, and the address decoded by the '139 as "ROM"/OE.

Of course, with all these extra pins figuring out what it's doing is going to be all kinds of extra fun. Especially because we already know that the output value changes on subsequent reads.

Pin 1: CPU (Pin 40) -- but pin 40 on the CPU should be +5V?
Pin 23: NC? -- by context, if it were going to connect to anything, it'd be PRG1/2/CPU A11 (pin 23/23/15)

lidnariq wrote:
what are those two diodes (1S1588) doing?
D1: clamps PPU A9 to not exceed +5V
D2: clamps PPU A8 to not exceed +5V

... I wonder why?


lupin3rd wrote:
Oh, I also re-ran the Characterization test again, but on the master side this time.

With all dips OFF - System reported DIPSWITCHES: 00 00
With all dips ON - System reported DIPSWITCHES: 18 FC

Just thought I'd follow up and mention that. :)
Oh, good! This makes perfect sense now.


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PostPosted: Tue Sep 13, 2016 5:12 pm 
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Location: Evansville, IN
I was pretty tired when I was working on this late last night -- so I might have a few minor mistakes. I tried to be as accurate as possible, but on the pins that are marked "NC" and "NC?", maybe I just wasn't able to trace them down. I plan to review them, and post an update in the next day or two. Personal stuff is keeping me a little too busy. :)

I'll check on the questions you asked and try to firm up the details soon. Did I forget anything? You said to ignore the 74LS373, so I did -- but it may fill a few of those gaps. If I have time and I'm not too tired, I may go ahead and run those lines down too, just to be certain.

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Chris

"Can I keep his head for a souvenir?" -Max


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