What It Tests
The correct behaviour is to reset the duty cycle sequencers but not the clock dividers, which will result in a click followed by silence.
The behaviour implemented by most emulators is to also reset the clock dividers, which will result in a continuous tone.
This ROM will not function correctly on clones with mixed-up duty cycles, but should work on all other hardware. It has been verified on a PAL NES.
How It Tests It
First, the pulse channel clock dividers are configured with a period of 260 CPU cycles and identical phase:
Code: Select all
; a = 0
sta $4002
sta $4003
sta $4006
sta $4007
jsr wait_4096
ldx #$81
stx $4002
jsr wait_256
stx $4006
Code: Select all
; a = 0
sta $4003
jsr wait_1024
jsr wait_256
sta $4007
If the clock dividers are also reset, the two will be 1284 cycles out of phase, which is way off the correct delay of 1040 cycles, and both are clearly audible.