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 Post subject: APU phase reset test ROM
PostPosted: Fri Jan 06, 2017 4:51 pm 
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This ROM tests the behaviour of the APU pulse channel phase resets when writing to $4003 and $4007.

What It Tests

The correct behaviour is to reset the duty cycle sequencers but not the clock dividers, which will result in a click followed by silence.

The behaviour implemented by most emulators is to also reset the clock dividers, which will result in a continuous tone.

This ROM will not function correctly on clones with mixed-up duty cycles, but should work on all other hardware. It has been verified on a PAL NES.

How It Tests It

First, the pulse channel clock dividers are configured with a period of 260 CPU cycles and identical phase:
Code:
   ; a = 0
   sta $4002
   sta $4003
   sta $4006
   sta $4007
   jsr wait_4096

   ldx #$81
   stx $4002
   jsr wait_256
   stx $4006

Then pulse 1 is started immediately, and pulse 2 is started 1284 cycles later:
Code:
   ; a = 0
   sta $4003
   jsr wait_1024
   jsr wait_256
   sta $4007

Since the first write is known to take place at the start of a period, pulse 1 is advanced floor(1284/260) = 4 sequencer steps before pulse 2 is started, thus putting them exactly 180 degrees out of phase. As both channels have been set to full-volume square waves, no sound is heard.

If the clock dividers are also reset, the two will be 1284 cycles out of phase, which is way off the correct delay of 1040 cycles, and both are clearly audible.


Attachments:
apu_phase_reset.zip [643 Bytes]
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PostPosted: Fri Jan 06, 2017 5:26 pm 
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Posts: 301
Thanks for the test rom!
As far as I can tell, I can't hear a single sound in Mesen.

Also, this revealed a bug in my NES 2.0 implementation - roms with both no CHR RAM & no CHR ROM would crash on load. So the test rom ended up testing 2 different things!


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PostPosted: Fri Jan 06, 2017 5:33 pm 
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Sour wrote:
As far as I can tell, I can't hear a single sound in Mesen.
Just to double-verify: On hardware, there's a clear popping sound before the silence.

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PostPosted: Fri Jan 06, 2017 5:39 pm 
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WheelInventor wrote:
Just to double-verify: On hardware, there's a clear popping sound before the silence.
Yup, I do hear that at the very start before the silence, should have mentioned it.


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PostPosted: Fri Jan 06, 2017 7:08 pm 
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Rahsennor wrote:
Since the first write is known to take place at the start of a period

Does this work only at power-up, or can you align the channel's periods anywhere? If the former, it may not work on a flash cart such as the PowerPak. If the latter, how does that work?


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PostPosted: Fri Jan 06, 2017 9:06 pm 
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tepples wrote:
Does this work only at power-up, or can you align the channel's periods anywhere? If the former, it may not work on a flash cart such as the PowerPak. If the latter, how does that work?

It works at any time, and the code is in the OP: set the period to zero and wait. The apu_mixer test by blargg uses the same technique, though his timing is 4 cycles off so his version isn't completely silent.


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PostPosted: Fri Jan 06, 2017 9:12 pm 
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Location: NE Indiana, USA (NTSC)
I know setting the period of a pulse wave to anything less than 8 mutes the channel. I thought it also froze the divider. I guess this might also be a test for that not being the case.


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PostPosted: Fri Jan 06, 2017 9:16 pm 
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AFAICT nothing can freeze or reset the divider. It reloads from the period registers on underflow and that's it.


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PostPosted: Sat Jan 07, 2017 4:01 am 
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tepples wrote:
Does this work only at power-up, or can you align the channel's periods anywhere? If the former, it may not work on a flash cart such as the PowerPak.
I've tested it on a powerpak and can confirm that it passed the test.

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PostPosted: Sat Jan 07, 2017 8:50 pm 
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Formerly Fx3
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Location: Brazil
Quote:
The correct behaviour is to reset the duty cycle sequencers but not the clock dividers, which will result in a click followed by silence.

RockNES has passed.


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PostPosted: Sun Jan 08, 2017 2:52 am 
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Location: Russia
I'm not sure this test work correct on flash-cartridges...
Here is Famicom AV (RP2A03H + RP2C02H-0 chips) captured video:

Everdrive-N8
InviteNES

P.S:
same thing on dendy. I've tested chip without swap dutycycles bug (TA-03NP1 6527P),
because it already installed on PCB, i'm lazy right now replace it to UMC UA6527P.


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PostPosted: Sun Jan 08, 2017 3:35 am 
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They're both correct. That click is all it's meant to do.


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PostPosted: Sun Jan 08, 2017 3:41 am 
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Yes, you're right, but i confused about gray screen on everdrive-n8.
What official games rely on this behavior? Want to hear difference between emulators.


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PostPosted: Sun Jan 08, 2017 4:11 am 
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Does the N8 leave any residue in ram if not manually cleared? I know powerpak leaves sprite garbage.

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PostPosted: Sun Jan 08, 2017 4:16 am 
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It's a good idea to give some indication when the test is running and when it has finished running (so that the user knows whether it loaded correctly, etc), like that "bleep" at the start and end of blargg's tests.

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