As you can really code any mapper in the CPLD, he has adapted the implementation to create an oversize GN-ROM kind of mapper with configurable H/V mirroring and optional battery backed 8K WRAM. He has left the MMC3's scanline counter in, as well.
We will be using this board for some releases next year.
I have some requests for information:
- How can we get assigned an iNES mapper number? Is there any procedure? Who's in charge of assigning iNES mapper numbers?
- How can we get emulator support? I've checked fceux source code and with some work I might be able to implement something working but I was wondering whether developers just wait for the fceux team to implement the proposed mappers or the fceux team expects developers to submit code to support the new mappers. I don't think it's difficult as the new mapper is just a mashup of features of existing mappers.
- Do you have any suggestions?
Here's the mapper specification, from the VHDL file:
Code: Select all
-- Allows using up to 128 megabits (64 CHR + 64 PRG), mapping banks -- with 32 KiB granularity for PRG-ROM and 8 KiB granularity for CHR-ROM. -- -- Registers: -- $8000: CHR bank (low byte) -- $8001: CHR bank (high byte) -- $9000: PRG bank -- $9001: Mirroring and RAM enable: -- * BIT0, mirroring: 0 vertical, 1 horizontall. -- * BIT6, RAM write enable: 0 allow writes, 1 prohibit writes. -- * BIT7, RAM enable: 0: RAM disabled, 1: RAM enabled.