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PostPosted: Fri Aug 10, 2018 12:39 am 
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Ah, verify and retry. I see. That makes sense.


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PostPosted: Fri Aug 10, 2018 1:11 am 
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Sumez wrote:
I'm curious about scenarios where it makes sense to bank switch outside of NMI, but also outside of timed code (ie. on a specific scanline, NMI guaranteed to not happen).
I'm guessing it would be related to a special case requiring you to read data from another bank? but I can't imagine a scenario where I really need to do that while rendering is turned on.

Reading data or code along normal execution. Say common code is bank 0, enemy 0-3 code is bank 1, enemy 4-7 is bank 2, etc. If you have enemy 2 and enemy 6 visible, then you naturally need to switch there to execute their logic.


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PostPosted: Fri Aug 10, 2018 3:13 am 
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I admit I only skimmed this, so apologies if this method is already here.

I write the intent of my bank switch to shadow RAM before I bank switch. At the end of my NMI, it reads the shadow RAM and does the intent unconditionally. I do this for MMC3, but I think it'd work for most mappers.

My understanding of MMC1 might be shaky having not used it, but I think this might even work for it. Suppose an NMI interrupts after say... the third write.

The NMI does whatever it will do, and then resets the shift register, loads the shadow RAM and does the five writes to swap in that bank that the code it interrupted was trying to swap in. It returns. The code does two more writes. Nothing happens because only the fifth write matters.

But nothing happening doesn't matter because the right bank is already in thanks to the NMI. This does mean you have to reset the shift register for every bank swap, but that's not that bad. Let me know if that's wrong!

For mappers where only one write swaps, you end up swapping in the bank that's already there (because the NMI already did it) in the worst case, but that also doesn't matter.

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PostPosted: Fri Aug 10, 2018 4:52 am 
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So, how do you reset the MMC1 register, so that it definitely jumps back to zero writes, no matter how many writes have already happened?

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PostPosted: Fri Aug 10, 2018 4:56 am 
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By writing a set high bit to $8000, right?

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PostPosted: Fri Aug 10, 2018 5:17 am 
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Right. I just had a look at my code again: I indeed have that in the beginning of the program flow.
It resets the whole mapper, including the general bank setup (which one is the fixed bank, which one the variable) and the mirroring.

Since there's probably no way to reset just the writes to $E000, I did the thing with the flag:

After the start, before any write to $8000 for the mirroring or $E000 for the bank, a variable in incremented and later decremented again.

If NMI hits and it detects that this variable is not 0, it immediately exits, even without updating the music. (Since music updates would require another bank switch.)

In my setup, I never try to correct incomplete MMC1 writes because I make sure that there can never be any incomplete writes to begin with.

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PostPosted: Fri Aug 10, 2018 5:32 am 
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If it really resets the mirroring a wiki update may be in order.

It says it rewrites Control OR $0C. That does force control to "fix last bank at $C000 and switch 16 KB bank at $8000", but that's how I'd personally have it set up anyway. If the wiki is right (and I'm understanding the wiki correctly), the mirroring doesn't change and neither does CHR ROM bank mode.

So you're correct that my method would not work if you preferred a different PRG mode (or switched at run time). Otherwise it might be fine. But code is king, so I'll just write a test ROM when I've got a minute.

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PostPosted: Fri Aug 10, 2018 5:35 am 
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Kasumi wrote:
If it really resets the mirroring a wiki update may be in order.

I'm not quite sure. I just suspected it, I didn't do actual tests.

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