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 Post subject: CNROM / Bits 4&5
PostPosted: Fri Apr 29, 2005 12:36 pm 
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Well, the 74HC161 chip is basically a 4 bit presettable counter, in the case of a NES mapper it's just used as a latch and the count option is never set (it was the easier way to get 4 flips-flops).

On a CNROM board, the outputs PRG D0 and PRG D1 are connected to the D0 and D1 '161 inputs, so the latches outpouts will "maitain" this value, this allow you to preset the CHR A13 and CHR A14 outpouts, in a software wiewpoint it allows you to swap 4 8kb CHR banks.

What about the two remaining latches, D2 and D3 ? They're connected to the PRG D4 and PRG D5, so, when writing to this mapper, not only the bits 0 and 1 matches, but the bits 4 and 5 are also connected to the mapper. I'm not totally sure of this, but the '161 outputs Q2 and Q3 are connected to CHR A11 and CHR A12. My question is : What does this means ?

For my wiewpoint, it would mean that writing, for example #$0x (where x is the CHR bank number 0-3) into the '161 mapper would only allow you to tiles $00-$7f in the first pattern table, and if the PPU is trying to read anything else, bus conflicts would appear. Here, if the '161 wons, it would just mirror the tiles $00-$7f in the first pattern table, else, if the PPU wons nothing particular would happen. Because thoose bus conflics could be here for the majority of the time, the '161 chip may simply burn.
To acess others tiles, writing another value into the mapper would be needed. For example, to read the tile section $00-$7f in the segond pattern table, writing #$2x in the mapper would be needed.
Of course, all this stuff above is a nonsense otherwise all the CNROM games out there wouldn't work. I tried to toggle thoose bits in emulation, but no emulators makes any diference.
Note : Some games does always clears thoose two bits, and others does always set them.

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PostPosted: Fri Apr 29, 2005 3:31 pm 
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Weird, that doesn't sound right. Is it really like that? I don't have a CNROM board to check at the moment. If it's true, then the CHR address lines must be 'winning' the (almost constant) bus conflict, it makes no sense to me either.

Only somewhat related, but MHROM also uses the 74HC161 and actually is set up to support 128kB PRG and 32kB CHR. SMB/DH only used 64kB/16kB though. With the same bit setup you mention, D0-D1 and D4-D5. D4-5 are for PRG in this case.


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PostPosted: Sat Apr 30, 2005 12:31 am 
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Yeah, it makes non sense.
I also have no CNROM games to check at the momment. I just based this on the Kevin Horton's "Cartidges Types" doccument. I'm sure that toose bits are connected to the mapper, because Gradius always set them (it writes $3x instead of $0x to the mapper). The doccument says CHR A11 control and CHR A12 control. I don't know what this would exactly means.

Normally, thoose bits could be connected to CHR A15 and CHR A16 to get up to 128kb CHR space.

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PostPosted: Sat Jun 11, 2005 9:53 am 
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Ah, I eventually got a card of Adventure Island Classic today and I'm checking all its connections !
Here you are :
'161 chip

1 (/master clear) : VCC (the latches are never clear, so emus wich emulates it to be reseted on system reset are wrong, it'll depend on the state of the flip flops)
2 (clock) : PRG /CE (pin 20)(will be clocked when the PRG is enabled and becomes disabled (???), anyway, the clock will never be used
3 (A input) : PRG D0 (pin 11), this is the LSB of the value you'll be writing to the mapper via $8000-$ffff. This connexion can be affected by bus conflicts !
4 (B input) : PRG D1 (pin 12), same as above for the MSB value
5 (C input) : VCC (this latch will always be set to an high value, but it could be used as a third bit for CHR selection)
6 (D input) : VCC (could be used for a fourth bit)
Those two input aren't connected to PRG D4 and PRG D5 at all. I don't know why Kevin horton's doc say it so
7 (CEP) : GND (the chip won't count even if clocked)
8 : GND
9 (/Load) : PRG R/W (the chip will be loaded if you're writing to it, and will latch when the CPU reads the PRG rom
10 (CET) : GND (don't count)
11,12 (Qd-Qc) : connected to a track wich goes up out of the board (provisions for extra logic ?)
13,14 (Qb-Qa) : connected to respectively to CHR A14 and CHR A13 (this is the actual bankswitching
15 (RCO) : Floating (not used because the thing doesn't count)
16 : VCC

I don't know why games does write something (usually the binary value of 1) in D4 and D5, so bakswitch number are $30, $31, $32, $33 intead of just $00, $01, $02, $03. Looks like PRG D4 and PRG D5 are not connected to any other thing than the cartidge connector, at least not on my card. If someone could check this on another board, that would be kind.
Another thing I noted is that there is two pads on the board, noticed SL and CL. The CL one does a contact between the PRG A14 and the cartidge connector. If we would put some solder on the SL one, it would tie PRG A14 to VCC and the PRG would be 16kb instead of 32kb.

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