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PostPosted: Wed Nov 09, 2005 6:00 pm 
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Why does Zelda "switch" VROM banks when it uses CHR RAM? Something to do with A13? It has no purpose whatsoever does it?


Last edited by kyuusaku on Wed Nov 09, 2005 6:10 pm, edited 1 time in total.

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PostPosted: Wed Nov 09, 2005 6:09 pm 
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On MMC1 (and even MMC3) cartridges with CHR RAM, the bank select line(s) are usually still connected to the mapper chip, allowing the RAM to be banked like normal. However, most games will just map in the default banks and leave them as-is (though some do not, such as the Famicom RPG 'Lagrange Point').

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PostPosted: Wed Nov 09, 2005 6:18 pm 
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The game isn't banking CHR RAM in "4k mode" though, its switching to bank 1 which I assume does absolutely nothing since in "8k mode", A0-12 are fixed. Am I missing something? Thanks


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PostPosted: Fri Nov 11, 2005 7:41 am 
Zelda only writes to $A000/C000 during the initialization code. The code first writes to all four addresses ($8000/A000/C000/E000) with bit 7 set (Reset port). It doesn't actually need to do this, as setting bit 7 has the same meaning regardless of what address you write to, but a number of games write it to all four registers anyway, most likely to be sure the MMC1 is reset properly. Zelda then writes to $A000 setting the register to zero, thus mapping CHR bank 0 from $0000-1FFF (since bit 4 of $8000 is clear). Again, not technically necessary since there's only one 8K bank, but it is still good programming practice to do so to avoid ambiguity. After these writes, Zelda never touches $A000 or $C000 again for the remainder of execution (near as I can tell, anyway).


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PostPosted: Fri Nov 11, 2005 9:27 am 
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This is definitely not needed, because I made myself a FF2 card, and I forgot to turn back the dummy bit to MMC1 registers done to modify the game to use mapper 2, I only did it for PRG and MMC1 mode registers, I forgot to do it for CHR registers, but the game still works fine. However, I think it should be done when the mapper is reseted scince all official MMC1 games using CHRAM does this.

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PostPosted: Fri Nov 11, 2005 9:31 am 
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FF2 on UxROM?

but UxROM has no SRAM


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PostPosted: Fri Nov 11, 2005 9:59 am 
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You know, the hacked version that use mapper 2 on witch the english translation was randomly based, there is about a fourty threads talking about that on both new and old board.
Of curse, UxROM has no SRAM, but it is only a hacked version, and because of this, everyone (including me in the past) think that FF2 is UNROM, even if it is SNROM actually.

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PostPosted: Fri Nov 11, 2005 11:23 am 
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Anonymous wrote:
Zelda only writes to $A000/C000 during the initialization code. The code first writes to all four addresses ($8000/A000/C000/E000) with bit 7 set (Reset port). It doesn't actually need to do this, as setting bit 7 has the same meaning regardless of what address you write to, but a number of games write it to all four registers anyway, most likely to be sure the MMC1 is reset properly. Zelda then writes to $A000 setting the register to zero, thus mapping CHR bank 0 from $0000-1FFF (since bit 4 of $8000 is clear). Again, not technically necessary since there's only one 8K bank, but it is still good programming practice to do so to avoid ambiguity. After these writes, Zelda never touches $A000 or $C000 again for the remainder of execution (near as I can tell, anyway).

I was looking at Zelda 1 for FC (1993 version) which I assumed is little different than the US game, I see now that it is after watching the US game. It writes $10 (oops, wouldn't be A13) and $00 to $A000, a lot.

Disch wrote:
FF2 on UxROM?

but UxROM has no SRAM

But on a Famicom copier it does, the MMC1 games hacked for UOROM are so that the older 1987 Famicom copiers could play the games, without trainers or bankswitching registers, only a UOROM like state.


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PostPosted: Fri Nov 11, 2005 6:49 pm 
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How much extra hardware would it take to modify a U*ROM board to take battery-backed SRAM?


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PostPosted: Fri Nov 11, 2005 8:02 pm 
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A 74'138, a 6264 and a CR2032, some passive components for healthy operation. It wouldn't be fun getting the SRAM on there though


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PostPosted: Sat Nov 12, 2005 1:48 am 
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Has anyone tested an NVRAM circuit with just passive components? I thought a controller was needed, to keep the RAM disabled when the power supply is out of the CPU's specs. Maybe the 'hold reset when shutting off' thing is a fix for that, though I'm not sure.


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PostPosted: Sat Nov 12, 2005 6:40 am 
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I'm getting outtopic, but who cares, right ?
So, I happened sometimes to forgot to press RESET while turning the power of on Zelda or Final Fantasy II, and I never happened to loose my saves. However, I happened to lose my saves in some SNES games, while they doesn't say to press the reset button, I still do it on my SNES now by precaution. However, Dragon Quest VI is the only SNES game as far I know to say to hold down the RESET button, I don't know why.

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PostPosted: Sat Nov 12, 2005 8:24 am 
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Memblers wrote:
Has anyone tested an NVRAM circuit with just passive components? I thought a controller was needed, to keep the RAM disabled when the power supply is out of the CPU's specs.

A controller is needed to map SRAM into CPU$6000. If you're prototyping it out of discrete logic, then you may also have a few gates to spare for extra write protection upon power cycle. I seem to remember in Nintendo Power's article about mappers that the MMC5 was the only MMC with robust power-down safety.


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PostPosted: Sat Nov 12, 2005 9:10 am 
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Just Breed stills says to press reset button while turning off the power.

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PostPosted: Sat Nov 12, 2005 12:22 pm 
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Can someone give an example of a protection in logic?


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