blargg's dmg_sound-2 tests in plain English
Posted: Mon Jan 11, 2016 3:50 pm
Can anyone decipher blargg's cryptic test ROM comments into plain English?
I'm trying very hard to pass his tests (I was able to pass 1-6), but I can't make any sense out of the rest. Sorry if it seems disparaging, I appreciate test ROMs very much, but I really wish they could be bothered to write more than six to twelve words to explain what each one is actually testing. The source code for test ROMs is usually even -less- helpful because it's full of 80 macros that hide what's really going on.
Also, I'm not one to talk. My test ROMs are even worse. I'm just frustrated because test ROMs aren't really helpful when they're indecipherable :(
Any help would, as always, be very much appreciated.
07-len sweep period sync: #5 "Powering up APU MODs next frame time with 8192"
I have no idea what he means by frame time. But in his source, I see this for NR52 writes:
He's resetting the frame_phase, which is the sequencer step (it goes through eight phases, which varyingly clock the lengths, sweep and envelopes.) I do the same thing as he does with frame_phase = 0, but still fail the test.
Also very bizarre is his bit-twiddling logic: "(data ^ old_data) & power_mask"
That basically causes the APU to reset itself both on 0->1 and 1->0 transitions.
I can't really believe that's how the real hardware works. Whether I do this or not, I still fail. It's just curious.
08-len ctr during power: "40 00 40 40 3cf589b4 Failed"
I'm not sure how this could be less intuitive if he tried.
09-wave read while on: <huge amount of zeroes> "7a 75e7b6 Failed"
See above. My understanding is wave RAM is always readable while on.
10-wave trigger while on: <about 30 pages of hex values that scroll off screen immediately> "Failed"
I stand corrected. Scrolling test results offscreen is even worse.
11-regs after power: #4 "Power off shouldn't affect NR41"
NR41 is the length value for square 1. I made it so that disabling the APU via NR52 doesn't affect it. The test still fails anyway. So there's more to this test than just that.
12-wave write while on: <about 30 pages of hex values that scroll off screen immediately> "Failed"
Sigh.
I'm trying very hard to pass his tests (I was able to pass 1-6), but I can't make any sense out of the rest. Sorry if it seems disparaging, I appreciate test ROMs very much, but I really wish they could be bothered to write more than six to twelve words to explain what each one is actually testing. The source code for test ROMs is usually even -less- helpful because it's full of 80 macros that hide what's really going on.
Also, I'm not one to talk. My test ROMs are even worse. I'm just frustrated because test ROMs aren't really helpful when they're indecipherable :(
Any help would, as always, be very much appreciated.
07-len sweep period sync: #5 "Powering up APU MODs next frame time with 8192"
I have no idea what he means by frame time. But in his source, I see this for NR52 writes:
Code: Select all
else if ( addr == status_reg && (data ^ old_data) & power_mask )
{
// Power control
frame_phase = 0;
for ( int i = osc_count; --i >= 0; )
silence_osc( *oscs [i] );
reset_regs();
if ( wave.mode != mode_dmg )
reset_lengths();
regs [status_reg - start_addr] = data;
}
Also very bizarre is his bit-twiddling logic: "(data ^ old_data) & power_mask"
That basically causes the APU to reset itself both on 0->1 and 1->0 transitions.
I can't really believe that's how the real hardware works. Whether I do this or not, I still fail. It's just curious.
08-len ctr during power: "40 00 40 40 3cf589b4 Failed"
I'm not sure how this could be less intuitive if he tried.
09-wave read while on: <huge amount of zeroes> "7a 75e7b6 Failed"
See above. My understanding is wave RAM is always readable while on.
10-wave trigger while on: <about 30 pages of hex values that scroll off screen immediately> "Failed"
I stand corrected. Scrolling test results offscreen is even worse.
11-regs after power: #4 "Power off shouldn't affect NR41"
NR41 is the length value for square 1. I made it so that disabling the APU via NR52 doesn't affect it. The test still fails anyway. So there's more to this test than just that.
12-wave write while on: <about 30 pages of hex values that scroll off screen immediately> "Failed"
Sigh.