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PostPosted: Tue May 30, 2017 12:26 pm 
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Hi,

I can't seem to find information regarding how 0xCB instructions are handled by the CPU when it comes to the Timer and Interruptions.
Meaning, is the 0xCB read as an instruction and then handles things etc, then it reads then ext instruction from the 0xCB table.

Or is 0xCB read and immediately afterwards the next byte is read, ignoring everything else until the entire instruction is complete?


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PostPosted: Tue May 30, 2017 4:08 pm 
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zerowalker wrote:
Hi,

I can't seem to find information regarding how 0xCB instructions are handled by the CPU when it comes to the Timer and Interruptions.
Meaning, is the 0xCB read as an instruction and then handles things etc, then it reads then ext instruction from the 0xCB table.

Or is 0xCB read and immediately afterwards the next byte is read, ignoring everything else until the entire instruction is complete?


Interrupts can't occur between the 0xCB prefix and the second byte. How would the CPU recover if they did? Think of the second byte as a special kind of operand, not as a separate instruction.


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PostPosted: Tue May 30, 2017 5:55 pm 
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AWJ wrote:
Interrupts can't occur between the 0xCB prefix and the second byte. How would the CPU recover if they did?

By storing the "0xCB occurred" bit in the status flags, like the HuC6280 does with prefix 0xF4.


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PostPosted: Tue May 30, 2017 7:21 pm 
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relevant


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PostPosted: Tue May 30, 2017 10:13 pm 
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A bit confused, don't really understand the relevant post (apparently a bit too low level for my understanding of these things i guess).

But as far as i know, there is no "0xCB" flag, at least not a visible one, which of course doesn't mean it doesn't exist at all.

So, is there a way to determine these things?

I assume in this case it's always read as a 2 byte instructions directly more ore less,
but as it was mentioned there is a case with a status flag, it means this isn't a rule for these kind of things.


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PostPosted: Tue May 30, 2017 10:19 pm 
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As far as I can tell:

0xCB on Z80 is atomic; there can be no interrupt between it and the instruction it modifies.
Prefixes on x86 are likewise atomic, and some instructions have enough prefixes to fill 15 bytes.
0xF4 on HuC6280, by contrast, is not atomic, instead setting an ephemeral status flag. I mentioned it as a contrast to the 8080-family way of doing prefixes.


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PostPosted: Tue May 30, 2017 10:31 pm 
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Ah, seen the word atomic used a alot and never been too clear on the meaning, except it seems to mean "close/directly by by the cpu" or something.

So that's basically what it is then, and atomic operation is completed by the CPU without any interference from whatever could interfere more or less?

And so there is basically no x86 non-atomic prefixes?
If so that's nice, makes things more simple:p


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PostPosted: Wed May 31, 2017 2:12 am 
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Quote:
and atomic operation is completed by the CPU without any interference from whatever could interfere more or less?
Yes.
Quote:
close/directly by
No. Some etymology should help…
wiktionary wrote:
atom
From Middle French athome, from Latin atomus (“smallest particle”), from Ancient Greek ἄτομος (átomos, “indivisible”), from ἀ- (a-, “not”) +‎ τέμνω (témnō, “I cut”).

atomic
Adjective
[…]
5. (computing) Of an operation: guaranteed to complete either fully or not at all while waiting in a pause, and running synchronously when called by multiple asynchronous threads.

Indivisible. Uninterruptible.


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PostPosted: Wed May 31, 2017 2:51 am 
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Ah thanks that clear things up, appreciated:)


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