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PostPosted: Wed Oct 25, 2017 6:20 am 
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Regarding this Gameboy CPU (LR35902) Instruction Set table, the CB prefix is marked as 4 T-cycles, but the Prefix CB table cells contain their own timings. Does that mean that the total time is 4 + X T-cycles, where X comes from the Prefix CB table?

Also, instructions E2 and F2 are listed as length 2. Are those typos?


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PostPosted: Wed Oct 25, 2017 7:50 am 
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zeroone wrote:
Regarding this Gameboy CPU (LR35902) Instruction Set table, the CB prefix is marked as 4 T-cycles, but the Prefix CB table cells contain their own timings. Does that mean that the total time is 4 + X T-cycles, where X comes from the Prefix CB table?

No, it looks like the total time will be whatever's listed in the CB table; it's just that it takes 4 cycles to read the CB prefix and switch into CB mode or whatever, which is why something like SLA A (for example) ends up taking 8 cycles total, even though the actual shifting only happens in the latter 4.

zeroone wrote:
Also, instructions E2 and F2 are listed as length 2. Are those typos?

I'm fairly certain they are.


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PostPosted: Sun Oct 29, 2017 8:41 am 
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Thanks.

Also, are the BIT n,(HL) instructions 12 or 16 T-cycles in length?


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PostPosted: Sun Oct 29, 2017 5:31 pm 
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I can't speak authoritatively, but both the pandocs and the gambatte source code claim it's 12. It makes sense that they'd take less than RES (HL), or SET (HL) too, since they don't do any sort of writeback.


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PostPosted: Mon Oct 30, 2017 4:36 am 
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zeroone wrote:
Also, instructions E2 and F2 are listed as length 2. Are those typos?


Yes, they are definitely only one byte long.


zeroone wrote:
Also, are the BIT n,(HL) instructions 12 or 16 T-cycles in length?


Should be 12. At least I implemented them with 12 and that passes Blargg's tests.
And it fits the 3 memory reads the instruction performs.


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PostPosted: Mon Oct 30, 2017 9:34 am 
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RĂ¼diger wrote:
Should be 12. At least I implemented them with 12 and that passes Blargg's tests.
And it fits the 3 memory reads the instruction performs.


Concerning Blargg's timing tests, is it sufficient for the emulated CPU to wait the instruction length in T-cycles and then carry out the instruction atomically, or does it need to process instructions incrementally, one microcode at a time. There are some instructions that perform multiple reads and multiple writes. For the timing test, does that need to be spread out over those T-cycles or can it all be done on the final T-cycle?


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PostPosted: Tue Oct 31, 2017 2:33 am 
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zeroone wrote:
Concerning Blargg's timing tests, is it sufficient for the emulated CPU to wait the instruction length in T-cycles and then carry out the instruction atomically, or does it need to process instructions incrementally, one microcode at a time. There are some instructions that perform multiple reads and multiple writes. For the timing test, does that need to be spread out over those T-cycles or can it all be done on the final T-cycle?

The memory timing tests will require the read/writes to happen on the correct T-cycles, for the others I don't believe it matters.


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PostPosted: Tue Oct 31, 2017 5:16 am 
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If you want to also pass my test ROMs at some point, you'll need fine-grained timing. :twisted:
...I'm just going to leave this here: https://github.com/Gekkio/mooneye-gb#ac ... comparison


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PostPosted: Tue Oct 31, 2017 7:12 am 
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gekkio wrote:
If you want to also pass my test ROMs at some point, you'll need fine-grained timing. :twisted:
...I'm just going to leave this here: https://github.com/Gekkio/mooneye-gb#ac ... comparison


Are any games actually affected by a lack of "fine-grained timing"?

Is there a microcode reference that I can use to improve the timings? I.e. how do you know what happens on each M-cycle or each T-cycles?


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PostPosted: Tue Oct 31, 2017 8:21 am 
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zeroone wrote:
Are any games actually affected by a lack of "fine-grained timing"?


Yes, but only like 5%-10% so you can get very far without worrying about this kind of stuff. And the important bits involve mostly other things than the CPU.

zeroone wrote:
Is there a microcode reference that I can use to improve the timings? I.e. how do you know what happens on each M-cycle or each T-cycles?


Unfortunately there's no single document that thoroughly covers fine-grained timing. My test ROMs include some comments that explain things like what happens during each M-cycle when there is something non-obvious going on (= internal M-cycles are involved, not just memory accesses).


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PostPosted: Tue Oct 31, 2017 8:45 am 
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gekkio wrote:
And the important bits involve mostly other things than the CPU.


Yikes! What are some of those things and do test ROMs exist to expose them?


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PostPosted: Tue Oct 31, 2017 8:54 am 
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Parts of the Game Boy SOC outside the LR35902 core include PPU, APU, timer, and serial. Parts of the running Game Boy outside the SOC include the MBC.


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PostPosted: Tue Oct 31, 2017 9:39 am 
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tepples wrote:
Parts of the Game Boy SOC outside the LR35902 core include PPU, APU, timer, and serial. Parts of the running Game Boy outside the SOC include the MBC.


Yep. But, what are some specific issues that I'm probably going to encounter first? I'm just trying to gauge if I should attempt this :)


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