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 Post subject: Verilog MBC5
PostPosted: Sat Jun 09, 2018 5:37 pm 
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Location: Fort Wayne, Indiana
Code:
module MBC5
  (
    input not_reset,
    input not_cs,
    input not_wr,
    input [7:0] data,          // data bus value
    input [3:0] address,       // top 4 bits of address
    output [8:0] out_rom_bank, // 9-bit ROM bank to use
    output reg [3:0] ram_bank, // 4-bit RAM bank to use
    output out_ram_enable      // active low RAM enable
  );
  reg [8:0] rom_bank;        // currently selected ROM bank
  reg ram_enable;            // is RAM enabled?

  always@(posedge not_wr or negedge not_reset) begin // may need negedge instead?
    if (!not_reset) begin
      ram_enable <= 0;
      rom_bank <= 0;
      ram_bank <= 0;
    end
    else if(!not_wr) begin
      case(address) // select based on top 4 bits of address
        0, 1:
          ram_enable <= data == 8'h0a;
        2:
          rom_bank[7:0] <= data;
        3:
          rom_bank[8] <= data[0];
        4, 5:
          ram_bank <= data[3:0];
        // anything 6 or above ignored
        endcase
     end
  end

  // select fixed bank or switchable bank
  assign out_rom_bank = address[2] ? rom_bank : 0;
  // select external RAM at 0xA000 - 0xBFFF
  assign out_ram_enable = !(ram_enable && address[3:1] == 3'b101);
endmodule

I don't know if the lack (is there one? Tepples keeps mentioning it) of >32KB Game Boy boards is because of a lack of open MBC implementations or some other reasons, but I really doubt it's a cost problem because the parts to implement a mapper are so cheap. In any case, here's a (public domain) MBC5 I wrote, that works in simulation at least. I'm not entirely confident in the clocking being correct, or what the reset values should be, but it should hopefully only require minor changes. It easily fits in an Xilinx XC9536XL, using 24 of the 36 macrocells.


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 Post subject: Re: Verilog MBC5
PostPosted: Sat Jun 09, 2018 5:52 pm 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 7212
Location: Seattle
Of all the MBCs, even the MBC5 is really quite simple; it's almost something you can build in discrete 74xx logic (QFN parts) and fit inside a DMG shell.

My hunch is what is holding back DMG carts is
1- People like DIP; DIP is mostly a nonstarter to fit inside existing DMG shells.
2- People mostly don't have nostalgia for the original DMG games (which were mostly 5V-friendly 512 KiB and smaller) but instead for the larger GBC carts, and then you have the problem of fitting a 3V ROM and logic translation inside a shell


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 Post subject: Re: Verilog MBC5
PostPosted: Sat Jun 09, 2018 5:55 pm 
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Joined: Sun Sep 19, 2004 11:12 pm
Posts: 20159
Location: NE Indiana, USA (NTSC)
Catskull's GB flash cart is 32K. That's not quite big enough for even a game of similar scope to the first Super Mario Land. There's plenty of room for homebrew to grow from 64K to 512K as the scene grows. And some GBC-era games are still 512K or smaller: Elmo in Grouchland, for instance, is 256K of game plus 768K of irrelevant padding.

The equivalent of UNROM/UOROM would be about two chips: a latch and a quad OR. This would allow up to 256K. And the presence of separate read and write signals on the GB cart edge means bus conflicts might be easier to avoid, allowing the cart to present a port at $2000 that allows use of a ROM on both an MBC (for emulators) and the discrete hardware. The MBC would decode the port at only $2000-$3FFF or $2000-$2FFF, with the rest devoted mostly to SRAM selection, while the simplified hardware decodes the port across all of $0000-$7FFF.


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 Post subject: Re: Verilog MBC5
PostPosted: Thu Jun 14, 2018 1:15 am 
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Posts: 7212
Location: Seattle
tepples wrote:
The MBC would decode the port at only $2000-$3FFF or $2000-$2FFF, with the rest devoted mostly to SRAM selection, while the simplified hardware decodes the port across all of $0000-$7FFF.
That really doesn't actually save you much: just decoding $2000-$2FFF vs all of $0000-$7FFF is 4 ICs vs 3 ICs.
Limit the size to 256 KiB and that only takes 2 ICs.
Drop standard MBC 16F+16 banking and you can get down to 1 IC and back up to 512 KiB. (And as memblers pointed out with GTROM, one can emulate 16F+16 at programming time given a double-size ROM anyway).

I actually already have an eagle schematic/board for the four 74xx version. Fits in the standard cheap (5cm)² bulk-orderable PCBs. Never bothered to have it made because the routing was ugly.... and now you can't buy M29F160s anymore.

(edit) Gekkio says that in the original DMG, /CS arrives ½ master cycle after A14, so I should see if that's true in GBC/GBA also. If so, I could get away with just a 74'161 for a super-cheap self-flashable option...


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 Post subject: Re: Verilog MBC5
PostPosted: Mon Jun 18, 2018 11:45 pm 
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Posts: 764
A couple of issues I see from my own testing, the ROM bank should be set to 1 on reset, not 0, and the ram enable decoding isn't quite right. You forgot to include the not_cs input, and the decoding actually only cares that A14 is low (rather than A15:13 = 101).

Code:
assign out_ram_enable = cs || !ram_enable || address[2];


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 Post subject: Re: Verilog MBC5
PostPosted: Mon Jun 18, 2018 11:52 pm 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 7212
Location: Seattle
qwertymodo wrote:
the decoding actually only cares that A14 is low (rather than A15:13 = 101).
Per what Gekkio said, /CS is asserted for the memory range from $A000-$FDFF. On the DMG, it's specifically asserted after the first half master cycle, for the remaining 3.5 master cycles.

Other that timing difference, at least on DMG, there's no functional difference between (/CS=0 AND A14=0) and (A[15..13]='b'101).

Obviously Gekkio's data only concerns the DMG; the GBC and GBA's timing and ranges need to be compared.

... also, those linked timing graphs are subtly different from their graphs in their Complete Technical Reference.


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