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PostPosted: Mon Oct 15, 2018 5:33 pm 
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Joined: Mon Apr 13, 2015 7:52 am
Posts: 7
i see opcode halt about http://www.devrs.com/gb/files/faqs.html#HALT

There is such a description.
------------------------------------------------------------------------------
HALT operates differently depending on whether the Interrupt Master Enable (IME) is set or reset.
Assembly command EI sets IME to 1.
Assembly command DI resets IME to 0.
IME = 0 - [$ff0f].AND.[$ffff] = 0 :
HALT is aborted. Next instruction is executed normally.
If IME is set to 1 at a later time then a halt condition
will occur one instruction after IME is set to 1 to complete
the halt that was not allowed to finish earlier.
------------------------------------------------------------------------------
If the description is correct... emm..

At IME=0, [$ff0f].AND.[$ffff] = = 0
If DMG executes halt, it will not cause a pause.
In this case, DMG will continue to execute instructions after halt?


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