insidegadgets wrote:~WR – if low(grounded) and if RD is low, we can write to the SRAM and load a ROM or SRAM bank
That's a little misleading. It's not really "loading" anything.
how am I suppose to write the rom bank number if the 16 bit address bus is suppose to be used to write 0x21 ?
because the address bus isn't used to write anything? Try to forget anything that you've read anywhere that had the "A23" signal on it. That
entire diagram is exclusively for the GBA, and has little to do with how the DMG/GBC works, and it will just confuse you if you keep remembering it.
Let's talk about how old ROMs work.
There's a fixed number of pins that export data from the ROM. It's very often eight, almost always a power of two. This group of pins is usually connected to a data "bus", so that another device (like a CPU) can use its output.
There's some number of pins that can select what data to read from the ROM. There can be any number of them. These are called "address" pins because they let another device select what data to retrieve.
A closely related device is a RAM. It's almost the same, except that another part can put values
into it as well as get values out of it. In order to specify which, the CPU (or other device, as appropriate) has a variety of "control" signals that specify what action should happen.
When the number on the address pins is the number X, and the control signals specify that it wants to read from ROM, the ROM will drive the number stored at address "X" onto the data bus.
So how does the CPU say that it wants to read a value from address X? By driving the address bus with X, leaving the data bus undriven, and driving the control signals to say it wants to read now. Different CPUs use different conventions for "I want to read now", but in the Game Boy, it does this by either driving A15 or /CS low and then driving /RD low. The CPU must stop asking the external part to drive the data bus before the CPU wants to drive it.
Similarly, the Game Boy says "I want to write now" by driving either A15 or /CS low, and then driving /WR low. The CPU must stop asking the external parts to listen to a write before the CPU changes the contents of the address or data bus.
But, you say, many Game Boy games are bigger than 32 KiB. How does this work? Well, the ROM works the exact same way as before. It still has a bunch of physical address pins, each of what doubling the amount of data that can be talked about. But the Game Boy CPU can't drive those higher address lines directly, so something else has to control them.
The final and most vital part to understand is that
two different devices can be at the same address.
The Game Boy uses this extensively. The ROM can be read at one set of addresses – $0000 through $7FFF – but there are also control registers that do things when the CPU writes to the same addresses.
The "gbdev" wiki link explicitly calls this out, by specifying which addresses control the extra address lines to the ROM. So,
for the MBC1, if the CPU writes to address $2000, it will change the address lines seen by the ROM. This allow the CPU to view a movable "window" out of the ROM.
Do you have a coherent image of how things work now?
) bit address bus, how am I suppose to write the rom bank number if the 16 bit address bus is suppose to be used to write 0x21 ? If you open the link from insidegadgets and search "Read the next ROM bank (4000 – 7FFFh)", you will see he changes the 8 bit data bus from input to output is this because he is reading a gameboy game then(F1Race)?
(maybe luck with wire and code)