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PostPosted: Tue May 07, 2019 7:50 am 
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Location: NE Indiana, USA (NTSC)
supercat wrote:
If one needed 128KB+32K of ROM and 8K+8K of RAM to produce a super awesome game that couldn't possibly be done with fewer resources, so be it, but a programmer who used such resources on a game that could have been implemented as 8K+0K of ROM and 0K+0K of RAM would not have been appreciated (though I don't know that any historical games ever went below 32K+8K).

The smallest licensed Famicom game is Galaxian: 8K PRG ROM + 8K CHR ROM. The smallest licensed NES games are Donkey Kong and the rest of the launch lineup: 16K PRG ROM + 8K CHR ROM.

The smallest homebrew NES game I'm aware of is Magic Floor: 4K PRG ROM + 0K CHR ROM, using mapper 218 to repurpose half of nametable memory as 64 tiles' worth of CHR RAM. I'd bet Munchie Attack (4K PRG ROM + 8K CHR RAM) and Hot Seat Harry (1K PRG ROM + 8K CHR RAM) could be ported to mapper 218 if someone tried.

On the other hand, using the absolute minimum resources to make a given game isn't always the best option. It can be wise to spend more bytes on presentation to leave a better impression on the player. My Game Boy port of Magic Floor, for instance, adds a bunch of features, such as more detailed character animation, an animated demo, distinct textures for the floor cells and border, and achievements. And though Tetris could have been done in 4K, both Tengen and Nintendo saw fit to add cut scenes and the like to fill 32K PRG ROM + 16K CHR ROM.

One practical problem with fusemap recompilation as a web service is that obtaining synthesis software for old Xilinx FPGAs, such as the one in the PowerPak, is a pain.

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PostPosted: Tue May 07, 2019 10:10 am 
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Joined: Thu Apr 18, 2019 9:13 am
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tepples wrote:
One practical problem with fusemap recompilation as a web service is that obtaining synthesis software for old Xilinx FPGAs, such as the one in the PowerPak, is a pain.


For FPGAs, that's likely true, and I don't know what if anything can be done about that unfortunate situation. CPLD fusemaps tend to be fairly simple, though. If one has a fusemap for a mapper, and knows which rows and columns are associated with which nodes, it should be straightforward to compile a device with logic assigned to prevent nodes from being optimized out, blank out the fuses associated with those nodes, and then fill in fuses according to requested configuration options without needing to use vendor tools. If people targeting a CPLD use the CPLD during development and the game is any good, someone with FPGA tools should be able to process the translated version into an FPGA fusemap.


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