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PostPosted: Sat Oct 05, 2013 1:20 pm 
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I haven't done any 68k coding in a while, but judging by some instruction timing lists I'd say they'd be relatively close if they were clocked at the same frequency.


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PostPosted: Sat Oct 05, 2013 2:47 pm 
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http://emu-docs.org/NeoGeo%20Pocket/CPU ... _cpu_6.pdf

According to this document that I found, it looks like it takes 1 state to access 8 bits, and 2 states to access 16 bits. How does this work with a 16-bit bus?


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PostPosted: Sun Oct 06, 2013 2:07 am 
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IIRC, 16-bit accesses on a 16-bit bus don't incur an extra state on the TLCS-900, unless the address is unaligned (i.e. odd).


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PostPosted: Sun Oct 06, 2013 4:28 am 
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I think the bus accesses 16-bit memory in 2 states, but internally multiplexes it behave like a 1 state 8-bit bus, and uses an instruction buffer so it can read the first byte of an odd-aligned instruction without redundant memory accesses.


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PostPosted: Sun Oct 06, 2013 4:58 am 
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Quote:
and uses an instruction buffer

There's a 4-byte instruction prefetch queue. I've written some test ROMs that test the NGPC's prefetch queue and data buses. You can find them here.


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