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PostPosted: Wed Sep 10, 2014 12:55 pm 
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Hey guys, I've been tinkering with Genny carts, and i've got a couple questions on how the system handles the rom and ram.

Basically, the CPU can handle up to 4MB of ROM space, and in a cart without any SRAM that is exactly how it is wired --- All address lines run to the cart edge and it can read up to a 4MB (one 32Mbit rom chip) game. But, when SRAM is introduced, they split the rom into 2x 2MB pieces on different rom chips, and then map them using a combo of 74*139, 74*00 and 74*74 chips.

In testing to determine why this is, I have tried wiring a single 32Mbit rom into a cart that normally would only handle 16Mbit and ran the extra address line to the cart edge. The game will not boot. In this case I am using the same title as what was originally on the cart (NHL96, buffered to fill the chip). It appears that the decoder (74*138) enable on pin1 is connected to cart edge B9 (A21), which is where the rom chip's highest line needs to go to. If i hook up the decoder to say A20 instead, the game will boot but I cannot save, and with the decoder connected to A21 along with the rom the game will not boot at all.

TL;DR - How can a 32Mbit game be used in a Genny cart without having to bankswitch rom and ram on A21?


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PostPosted: Wed Sep 10, 2014 1:41 pm 
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Transcribe the circuit of 7400-family parts and you'll know the answer.

Or if you'd rather, post some good pictures of the PCBs and I'll do it for you.


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PostPosted: Wed Sep 10, 2014 8:13 pm 
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Here are a couple pics of the 2x rom board I'd like to get into one chip. Its running World series baseball '96 on this one.

Here are a couple links to the full size pics:

Here

and here


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PostPosted: Wed Sep 10, 2014 8:30 pm 
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The reason for this is that SRAM can be hidden. More specifically, for games with more than 2MB of ROM, there's a portion of ROM that overlaps where SRAM would go ($200000-$20FFFF), so they added a toggle to bank switch that portion between ROM and SRAM. That's where the 74xx chips come into play. The register that toggles between both portions is at $A130F1 (these games generally just look at the /TIME signal (the entire $A130xx range) unless they feature a full-blown mapper). Note that this usually switches the entire upper 2MB, not just the SRAM area (which makes things easier to implement).

For games with 2MB of ROM or less, there isn't an overlap, and there you would use a 74xx chip just to invert the chip enable signal for one of the ICs =P (so one gets enabled in the $000000-$1FFFFF range and the other in the $200000-$3FFFFF range)


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PostPosted: Wed Sep 10, 2014 9:51 pm 
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Looking closely at the pictures ... I don't think I'm going to be able to actually RE the circuit. Certainly /TIME is connected to 74HC74.↑1CLK, and /RST is connected to 74HC74./1RST

Assuming Sik's description is sufficiently accurate, if the game will work with ROM always mapped in lieu of RAM ... a replacement using a 2 MiB 'PROM and no RAM should be able to work just by not connecting 68000.A20, and instead connecting 68000.A21 → 'PROM.A20.

Otherwise, I don't think you can get the logic any simpler than the three ICs they're already using—although it's possible some of them could be converted to smaller forms with one or two gates instead of two or four.


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PostPosted: Thu Sep 11, 2014 12:36 pm 
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Ok that's kind of what I figured. It didn't make sense otherwise for them to choose to use 2x roms when 1 would be easier and cheaper to assemble. But if the SRAM is in the same space as the ROM then it'd need bankswitching.

That being said, and this may be a silly question, is there a way to implement that same bankswitching by toggling the highest address line on one ROM chip? So that the system can still use the A21 space for the RAM, then disable it and enable the A20 line on the ROM when it needs it? Maybe a CPLD design?


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PostPosted: Thu Sep 11, 2014 2:05 pm 
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Certainly possible. Not clear how many gates it would take. I'd like the actual schematic first. (Do you have a multimeter or even just a continuity meter?)

I'd assume the current thing is something like:
Half the 74'139 decodes 0x000000→0x1FFFFF and 0x200000→0x3FFFFF. The lower half just goes straight to one of the ROM's /CE, and 68000's /RD goes to both ROM's /OE and RAM's /RD.
Half the 74'74 latches some signal—could be anything from D0-D15 or A0-A7—whenever /TIME is asserted, i.e. reads or writes from 0xA13000→0xA130FF. (the other half is unused)
The output of that latch goes to the other half of the 74'139, and that enables either the second ROM or the RAM when reading/writing from 0x200000→0x3FFFFF.
Maybe the 74'00 combines /LDS with the above select signal for the RAM?


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PostPosted: Thu Sep 11, 2014 7:55 pm 
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I've got a multimeter. I'll try and draw out where things go this weekend.

I'll update here as soon as I've got some info


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PostPosted: Fri Sep 12, 2014 2:26 pm 
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Equivalent of this is going on in 4MByte + SRAM carts.

Image

Write to A130xx range pulses !TIME pin, that is used to latch the value of D0 line which controls whether or not upper 2MBytes are ROM or SRAM. 1 = RAM, 0 = ROM.

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PostPosted: Fri Sep 12, 2014 2:56 pm 
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May be a silly question, but where does the /TIME signal come from? I can't find reference of it on any pinout specs.

EDIT: Nevermind, you're referring to the clock signal. Got it.


Last edited by getafixx on Fri Sep 12, 2014 5:17 pm, edited 1 time in total.

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PostPosted: Fri Sep 12, 2014 4:24 pm 
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/TIME is NOT clock.
It's pin B31, and is low when the CPU accesses 0xA13000 through 0xA130FF.

Also, TµEE's schematic doesn't tell me what the 74hc00 is doing there?


Anyway, whatever the actual schematic is, you should be able to add a single AND gate (74'08) to combine the two ROMs' output enables to use a single ROM IC, if that's what you were originally asking.


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PostPosted: Fri Sep 12, 2014 5:13 pm 
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lidnariq wrote:
/TIME is NOT clock.
It's pin B31, and is low when the CPU accesses 0xA13000 through 0xA130FF.

Also, TµEE's schematic doesn't tell me what the 74hc00 is doing there?


Anyway, whatever the actual schematic is, you should be able to add a single AND gate (74'08) to combine the two ROMs' output enables to use a single ROM IC, if that's what you were originally asking.


My bad... I just dug up an old schematic I had downloaded before and you're right of course, the other ones I looked up label it as an unknown pin. And the 74HC00 isnt used in all carts, but in mine is connects to the battery controller BA6162 pin 3 (which is CE1 on there), and also to the SRAM /CE. Other carts seem to skip this chip and hook the sram /CE right to the BA6162 pin 3.

I'll have to try that out and see if a 74HC08 does the trick. So if I read what you said right, I'd take both /OE from the board (one from a 32Mbit chip, and the other from the second socket) into one gate, and the output would go the /OE on the cart edge? And that would enable the full 32mbit?


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PostPosted: Fri Sep 12, 2014 5:40 pm 
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getafixx wrote:
the 74HC00 isnt used in all carts, but in mine is connects to the battery controller BA6162 pin 3 (which is CE1 on there), and also to the SRAM /CE. Other carts seem to skip this chip and hook the sram /CE right to the BA6162 pin 3.
Ah. It combines /CE with the battery IC's +CE to allow a 32768x8 SRAM to be protected, whereas normally they'd have to use some SRAM with two enables.

Quote:
I'd take both /OE from the board (one from a 32Mbit chip, and the other from the second socket) into one gate, and the output would go the /OE on the cart edge? And that would enable the full 32mbit?
... Maybe I'm confused, what exactly are you trying to do?
Is it "use a single 4MiB/2MiW ROM on a board while retaining this battery-backed save RAM" ?
In that case, you'd use either socket—as far as I know, all of D0…D15 and A1…A19 are connected to both—and connect the new PROM's /CE from the output of the 74'08. You may also need to connect A20 and A21 from the cartridge edge to the PROM.

i.e. ROM1 has /CE
and ROM2 has /CE
and you want something that is low if either are low.


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PostPosted: Fri Sep 12, 2014 9:27 pm 
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lidnariq wrote:
Ah. It combines /CE with the battery IC's +CE to allow a 32768x8 SRAM to be protected, whereas normally they'd have to use some SRAM with two enables.

Yeah, the register $A130F1 (what you'd officially write to if you had a full blown mapper) has this format: ??????WE, where W = allow writing and E = enable SRAM (it needs to be 00 to make SRAM hidden and 11 to make SRAM writeable).


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PostPosted: Fri Sep 12, 2014 9:46 pm 
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Oh, so both bits in the 74'74 are used? And the 74'00 ... is used as two AND gates, for RAM /CE and /WR ?
And it's actually latching D8 and D9? (Or are you supposed to use byte-wide access only?)


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