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PostPosted: Sun Nov 15, 2015 7:39 pm 
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[OVERVIEW]
I successed digital video outputs for PCEngine. It uses real hardware, no modification, no AD converter.
CD excluded PCEngine system has EXTBUS. It contains full CPU buses and dotclock and color RAM address bus(VDC data).
I've researched them, EXTBUS outputs perfectlly digital video data before DA convert by VCE(6260).

I designed interface the PCB between EXTBUS and Terastic's Cyclone V development board(c5g).
The FPGA watches write cycles for VCE register, stores VDC data into internal RAM, outputs upscanned digital video to T.M.D.S encoder.

[Destinaion Display resolution]
VCE divides master clock as dotclock, the divide numbers 4, 3 or 2. Digital video needs fixed number multiply for the upscan. I design scanline multiply number is 3. The resolution are XGA (1024x768) and 720p (1280x720). It is async outputs, FPGA uses single frame buffer, the tearing happens about every 6 seconds. The player dont mind the tearing, it is the ideal spec...

I have tried full sync digital video output. I have not successed, it maybe requires modify to output master clock into external side. If FPGA gets PCE master clock, it can outputs stable T.M.D.S waveform, the LCD monitor won't display clarity. Because the video signal is non-compliant XGA. Full synced pixel clock is 21.47*3MHz, XGA requies 65.0MHz.

[confirmed software]
I checked about 30 HuCard games. Almost ganes works with clarirty video.

[next]
I will implement the backup memory system into the C5G.

(edit) added new photo.
- R-TYPE part2 (dotclock = master /3)
- TV sports bascketball (dotclock = master /2)
- Momotarou Densetsu Gaiden (dotclock = master /4)


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Last edited by naruko on Mon Nov 16, 2015 3:42 am, edited 1 time in total.
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PostPosted: Sun Nov 15, 2015 10:27 pm 
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This is great research. For me the tearing on-screen is a complete dealbreaker, but I am happy to see another system gain digital output.

For a zero-latency solution that won't tear, you could utilize the digital output from the EXTBUS and create a line doubler for a 2:1 video output.


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PostPosted: Mon Nov 16, 2015 6:08 am 
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Yes, looks very nice. It's basically the same idea as the NESRGB and other digital bus-sniffing mods.

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PostPosted: Sat Nov 21, 2015 7:56 pm 
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Some technical help, since you seemed to ask for it in a blogpost:

VCE Register $0400, bit 2 controls whether the video field is 263/262.5(?) lines (when 0/1.) When set to 1, it also has the intended side effect of composite artifact correction. This "correction" is not visible at all in RGB/digital signals:
Image

The only HuCard that I know of that sets $0400 bit 1 (512-pixel mode) is TV Sports Basketball. Several CD games use this high-res mode, though. If you have a PCE flash card, there are a couple screen test programs by me or others where you can do more thorough testing.

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PostPosted: Sun Nov 22, 2015 8:28 am 
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I understand what means display artifacts!
I will check Rastan Saga II, Volfied and OutRun.

I don't have a flash card. But my adapter PCB has 2pcs 32-DIP socket for 512k x8 SRAM and Flash. I can check your test program. ;)


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PostPosted: Sun Nov 22, 2015 11:40 am 
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ccovell wrote:
VCE Register $0400, bit 2 controls whether the video field is 263/262.5(?) lines (when 0/1.) When set to 1, it also has the intended side effect of composite artifact correction.

But does having the correction (i.e. interlace mode) also cause the screen to jitter up and down by a half pixel every frame?


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PostPosted: Sun Nov 22, 2015 5:58 pm 
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tepples wrote:
ccovell wrote:
VCE Register $0400, bit 2 controls whether the video field is 263/262.5(?) lines (when 0/1.) When set to 1, it also has the intended side effect of composite artifact correction.

But does having the correction (i.e. interlace mode) also cause the screen to jitter up and down by a half pixel every frame?

Sorry, my memory must be bad, then. Maybe it's 262. Charles Macdonald did some investigation into how this bit can be manipulated by software with accurate timing, to give "near-true" interlace, but as it is, either setting 262/263 gives noninterlaced video. IIRC, in 263 mode, the screen is higher by like 1/4 of a scanline.

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PostPosted: Tue Nov 24, 2015 4:50 pm 
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tepples wrote:
ccovell wrote:
VCE Register $0400, bit 2 controls whether the video field is 263/262.5(?) lines (when 0/1.) When set to 1, it also has the intended side effect of composite artifact correction.

But does having the correction (i.e. interlace mode) also cause the screen to jitter up and down by a half pixel every frame?


It does not happen. I do not think it is 262.5 lines but rather 262.

You can confirm this with Parasol Stars or Magical Chase, which are not interlaced yet does have the composite subcarrier movement (as opposed to Gekisha Boy or Pac-Land, which does not).


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PostPosted: Tue Nov 24, 2015 6:14 pm 
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The bit in the VCE reg controls whether the output is 262 or 263 scanlines - not half lines that I remember seeing on the scope. It also doesn't automatically switch between them on a frame by frame basis or such. The 263 mode simply allows the color burst phase to invert on the next frame, since every scanline flip-flops it (the phase) - having an odd amount of scanlines means it has the inverse pattern on the next frame and so on. For analog TVs without any fancy filtering, it allows the pixels (or rather, artifacts) to average over two frames (for still images).

Charles interlace trick is manually switching between 262 line mode and 263 line mode, at the right time - causing "fields" to overlap. IIRC, when you switch between the modes - it causes the current scanline to end (VCE scanline, not VDC pixel data) - timing is critical. The trick works great on SDTVs, but CRT HDtvs didn't like it. I suspect the lack of field identification equalization pulses might have something to do with it.

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PostPosted: Tue Nov 24, 2015 6:25 pm 
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tomaitheous wrote:
I suspect the lack of field identification equalization pulses might have something to do with it.
I think, more specifically, it's that the equalization pulses allow VSYNC to start in the middle of a scanline, whereas simpler NTSC generators don't bother.


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PostPosted: Sun Nov 29, 2015 9:20 pm 
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I have checked SuperGrafx with my 720p adapter.
The result is bad, SuperGrafx's EXTBUS is connected color RAM address by VDC #0. This is not connected to VCE directly.


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PostPosted: Mon Nov 30, 2015 12:50 am 
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And none of the VPC lines go out to the exp bus? (Well, why would they, the exp bus was designed before the SGX was...)

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PostPosted: Sat Dec 24, 2016 11:49 am 
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Is this the origin of the Upergrafx?


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