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PostPosted: Tue May 09, 2017 7:47 pm 

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19003
Location: NE Indiana, USA (NTSC)
In this post, Garth wrote:
My last major assembly-language project was on a PIC16 microcontroller which only has an 8-level return stack, and toward the end I was constantly overrunning it
(The PIC16 is really mickey-mouse compared to the 6502, BTW.)

But not Mickey Mouse enough to run Capade, Mania, and Epic.

But seriously:
Is the PIC16 also shoddier than the Intel 8080? We previously discussed its lack of useful indexed addressing modes other than moving the HL pointer around. Or the 8051? Are there criteria for what makes an architecture shoddy?

PostPosted: Tue May 09, 2017 9:15 pm 

Joined: Sun Mar 27, 2011 10:49 am
Posts: 186
You know, you've suggested that the 8080/LR35902/Z80's poor complement of indexed addressing modes are some kind of fatal flaw a few times since that discussion; not to get into some kind of 8-bit instruction set holy war - I love the 6502 - but one could easily argue that the 6502's register paucity, or its huge number of obviously "missing" instructions (push and pull X or Y, for instance), or the aspects of its design that make it a poor target for C compilers are similarly debilitating. In practice, just as one learns to make effective use of the programming model of the 6502 (say, keeping a convention of storing temporaries on zero page, or using the 6502's powerful addressing modes to implement a more flexible software stack), so too does one learn to work with the Z80's strengths and limitations with things like structs-of-arrays rather than arrays-of-structs and page alignment. The comparison of the Z80 - a sophisticated-for-its-time general-purpose CPU that was selected over the 6502 for many computers and video game platforms throughout the 8-bit era - to a primitive microcontroller like the PIC16 (an 8-deep stack! my god! just look at this instruction set!), just because it can be a little clumsy with random access on structs or non-page aligned arrays, is practically offensive :D

At any rate, to answer your question so as to make my response a constructive contribution to the topic at hand rather than just a rant, there's of course no precise definition of what makes an architecture "Mickey Mouse" or not, but a couple of obvious things that make could make it feel less powerful or less ergonomic that come to mind are inconsistencies (different registers having different capabilities, for instance) or deficiencies that present roadblocks with no obvious workarounds (say, an incredibly shallow stack). In general, if across the range of problems you need to solve you need to spend a higher proportion of your time thinking about and writing code to work around the CPU instead of dealing with the problem at hand, you'll get the impression that a CPU is "Mickey Mouse".

Or, in even more general, a CPU is "Mickey Mouse" if it makes your life difficult :)

PostPosted: Wed May 10, 2017 12:18 am 

Joined: Sun Apr 13, 2008 11:12 am
Posts: 6178
Location: Seattle
tepples wrote:
Is the PIC16 also shoddier than the Intel 8080?

As someone who has an almost irrational fondness of the 8-bit PIC family, it's pretty terrible.

It's roughly comparable to the 8051, but with the big plus of both constant and very low interrupt latency compared to almost all other microcontrollers.

There are 5 major groups in the 8-bit PICs:

12-bit instruction word PICs, originating with the very first parts (PIC1640, PIC1650, &c). A few of the "PIC12xxx" parts now. Intended to control peripherals on a CP1600-based (yes, the one from the Intellivision) computer. One pointer access port, eight other hardware definition registers, and 23 more bytes of RAM for 32 total "first class" addresses. Everything else has to be addressed indirectly (pointer register) or via banking. Usually only two entries in the call stack. Maximum program size without bankswitching is 9 bits→512 instructions. Doesn't always support interrupts.

"older" 14-bit instruction word PICs. Usually "PIC16xxx" parts. Adds a real call stack (the 8-call deep that Garth was complaining about) as well as more bits for RAM (7 bits now, making 128 bytes). Its prettiest form is the PIC10F322, which is as much as you can fit without bankswitching. Maximum program size without bankswitching is 11 bits→2048 instructions.

"traditional" 16-bit instruction word PICs. PIC18xxx. Three pointer registers, 9 bits for specifying 512 bytes of "first class" RAM, of which half is used as a dedicated access to the bankswitching interface and half is dedicated for an "access" bank providing faster access to the I/O registers and some RAM. Added a set of "shadow registers" such that interrupts wouldn't require saving or restoring the main thread's state. Maximum program size is 23 bits→8M instructions.

These first three were designed to be source-level compatible; a PIC12F508 program could be reassembled for a PIC18F452 with very few (if any) changes.

"newer" 14-bit instruction word PICs. Usually "PIC16xxx" parts. Adds a second pointer register, to increase the ease of targeting C to it. Moves the original fixed registers around so it's no longer source-level compatible. Started growing all sorts of fun peripherals. Also acquired shadow registers.

"extended" 16-bit instruction word PICs. Supported alternate mode in all but the oldest PIC18xxx. Redefines the meaning of the 96 bytes of "access bank" to instead mean pointer-relative, i.e. for fast access of variables on a C stack.

But, remember, the original design, and what it excels at, is high speed first-class access to its own peripheral controls. C compatibility is an afterthought, and it shows. But a native asm interrupt handler that can reliably do something in a constant 5 instruction cycles from the original event? Sure. And almost all instructions take the same amount of time to execute, so constant-time code is much more tenable.

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