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PostPosted: Mon Aug 27, 2018 1:52 pm 
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I was wondering if using a 5V tolerant CPLD in between a 5V and 3V bus would cause any issues. I don't see any reason why it would, but figured I'd throw the question here to see if anyone has any reason why that isn't a good practice.

Just seeing as a CPLD is needed for most custom mappers and such, if all the pins of a 3V chip were running through a CPLD that ran at 3V but is 5V tolerant (like the Xilinx 9500XL series), could it be good enough level translation that further shifters aren't needed?


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PostPosted: Mon Aug 27, 2018 2:00 pm 
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Correct, a 3V device with 5V tolerant inputs still emits its logical outputs at 3V, so are compatible with a subsequent not-5V-tolerant 3V device.


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PostPosted: Mon Aug 27, 2018 2:04 pm 
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lidnariq wrote:
Correct, a 3V device with 5V tolerant inputs still emits its logical outputs at 3V, so are compatible with a subsequent not-5V-tolerant 3V device.


But could it be used safely in reverse, to drive the NES data bus for example?

Code:
NES <---bidirectional---> CPLD <---bidirectional---> 3V ROM


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PostPosted: Mon Aug 27, 2018 2:10 pm 
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Safely, definitely, but possibly not compatibly.

The NES (and Genesis and Master System) all use so-called "5VTTL" voltage thresholds, which is compatible with "3VCMOS" thresholds.

The SNES (and maybe the Gameboy?) use "5VCMOS" voltage thresholds, which will not reliably receive a 3V as logic "1".

random blog post about this


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PostPosted: Mon Aug 27, 2018 2:12 pm 
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As long as the highs and lows are on each side of the threshold, i think it would. /regards, a hobbyist with no formal training.

Unlike the bad case where a 5v source is shorted with a diode to protect a 3.3v device, you're not putting strain on the 5v output (which is forced to provide a higher current than it was designed for in this situation).

lidnariq ninja'd me.

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PostPosted: Mon Aug 27, 2018 4:07 pm 
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Only problem I've found with that, is that it can get expensive per-pin compared to something like an LVC245. You probably already know this, but as far as CPLD resources, the inputs are "free", but each output pin will also use a macrocell. But if you have left-over resources, it seems like a fine way to use them.

Be aware that there is potential for some strangeness on the CPU data bus. I believe it's the OAM DMA causing a bus conflict, if the cart can output to the data bus too quickly. I don't think it's been fully investigated. If that happens, it's easy to fix by putting something like 300 ohm resistors in series with the data bus, between cart and NES. This has been known to happen on (at least) my old ROM emulator (with 74HC outputs), and the first version of the PowerPak had a similar problem.


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PostPosted: Mon Aug 27, 2018 11:53 pm 
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What is the point ? You're using a CPLD as a simple buffer to lower signal voltage (for "high" logic state) from +5V to +3V. You can do the same with a simple buffer/level shifter. Why bother use a CPLD at all ?


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PostPosted: Tue Aug 28, 2018 4:54 am 
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Because you have spare pins on the CPLD, and a level shifter is an extra item on the bill of materials.


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PostPosted: Tue Aug 28, 2018 9:09 pm 
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Bregalad wrote:
What is the point ? You're using a CPLD as a simple buffer to lower signal voltage (for "high" logic state) from +5V to +3V. You can do the same with a simple buffer/level shifter. Why bother use a CPLD at all ?


Tepples already answered below, but the idea is to use it instead of having to add additional costs to the PCB. Seeing as the CPLD is already a necessity (for NES, at any rate), might as well use it to do as many things as possible.

But like Memblers mentioned, bus conflicts and timing issues is something to avoid. Could use further testing, at any rate.


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