Wonderswan 2003 extended banking register width

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lidnariq
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Wonderswan 2003 extended banking register width

Post by lidnariq » Thu Jan 30, 2020 8:00 pm

The WonderSwan 2001 mapper IC has four banking registers, already well-documented:

I/O to port 0C0h: select 1MB bank (i.e. A20 up) in linearized x86 addresses 40000h-0FFFFFh
I/O to port 0C1h: select 64KB bank in linearized x86 address 10000h-1FFFFh
I/O to port 0C2h: select 64KB bank in linearized x86 address 20000h-2FFFFh
I/O to port 0C3h: select 64KB bank in linearized x86 address 30000h-3FFFFh

It's known that the 2001 only supports addressing 16MB of data, and the register at port 0C0h only implements 4 bits. (For readback too. The comment "All 8 bits hold state" in WSMan is wrong. Upper bits always read back as 0.)

In the 2003 mapper IC, two more address pins were added. While the above registers exist, and it's easy to extend the definition for the 1MB bank for this (and they did!), the other three bank select registers have already used up their full eight bits.

So they added mirrors with space for the extra bits!

I/O to port 0CFh: alias to port 0C0h. Value written in either can be read back from either. Six bits exist; upper two bits always read back as 0.
I/O to port 0D0h: alias to port 0C1h.
I/O to port 0D2h: alias to port 0C2h.
I/O to port 0D4h: alias to port 0C3h.

I/O to port 0D1h: control A24 and A25 during access to segment 1000h. Two bits exist; upper six bits always read back as 0.
I/O to port 0D3h: control A24 and A25 during access to segment 2000h. &c.
I/O to port 0D5h: same, segment 3000h.

It's clearly intended that 16-bit I/O access (e.g. out 0D0h, ax) is used on these expanded registers.

No games were released with more than 16MB of ROM, so this functionality is irrelevant.


In both the 2001 and 2003, all of the banking registers seem to usually power up holding all 1s. The Wonderswan IPL assumes this is true – it expects the ROM header to be found at 3FFFXh. The Wonderswan Color IPL explicitly writes FFh to both 0C2h and 0C3h before reading the ROM header from the same address.


One more piece of trivia related to the 2003: GPO pins disabled by writing 0 bits to port 0CCh both 1- have a weak pull-down on the physical pin, and 2- always read back as 0 from port 0CDh. Writes to 0CDh are still tracked even when the pin's output is disbled.

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