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PostPosted: Tue Feb 16, 2016 5:13 am 
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Tried with Metroid.
Have similar bugs:
https://youtu.be/WvDrO7akS1s
I'm out of ideas...
Where should I start searching? CHR RAM??


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PostPosted: Sun Feb 28, 2016 6:17 pm 
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I tried to decode PRG RAM address, ended with this circuit, using a 74ls08.
Attachment:
NES PRG RAM Decoder.png
NES PRG RAM Decoder.png [ 1.4 KiB | Viewed 950 times ]

It's working better, but in some rooms the platforms appear fine at first and then disappear or get mixed up.
Ocasionally some platforms or parts of the background change colors too.
Is this circuit implementation correct? I just used what I had at hand...
This seems to confirm my suspicions that it's kind of incomplete (or buggy) MMC1 clone.

I also tried to disable PRG ROM when writting PRG RAM using this circuit,(just added an 74ls04 to the mix) but ended with an unbootable cart:
Attachment:
PRG RAM Proteção.png
PRG RAM Proteção.png [ 1.43 KiB | Viewed 950 times ]

I'll try to do some videos showing what's up later.
Hope someone can give some advice this time...


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PostPosted: Sun Feb 28, 2016 7:18 pm 
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Fisher wrote:
Code:
    M2 --+---_
         |    )---+
/ROMSEL -+---¯    +--+---_
                     |    )--- PRG +CE
   A14 --+---_    +--+---¯
         |    )---+
   A13 --+---¯
[...]
Is this circuit implementation correct?
Looks right?

Note that /ROMSEL arrives later than M2, by enough to potentially be a problem.
It ought to be ok, but maybe as stands writes to the MMC1 register at $E000 could accidentally write to RAM as well.

You could try rearranging as

PRG RAM +CE = AND(AND(AND(M2,CPU A14),CPU A13),/ROMSEL) so that the propagation delay of M2 through the first two AND gates might match, and see if that fixes anything.

Quote:
Code:
          CPU R/W ------+---_
                        |    )---|>O--- PRG ROM /OE
 MMC1 PRG ROM /CE --|>O-+---¯
I'm not clear why that's not working? But it's worth pointing out that the PRG ROM should already be disabled (i.e. the MMC1 should already be generating MMC1 PRG ROM /CE = OR(NES /ROMSEL,NOT(CPU R/W)) )


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PostPosted: Mon Feb 29, 2016 12:36 pm 
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Thanks for the attention :-)
I have rearranged as you said and noticed no differences.
Should I add more logic to try to slow M2 down?
Maybe add a capacitor?

Fisher wrote:
(i.e. the MMC1 should already be generating MMC1 PRG ROM /CE = OR(NES /ROMSEL,NOT(CPU R/W)) )

I have tried it because I'm afraid that the RAM protection may not be implemented properly.
Maybe the LS04 I got is bad... I just got these parts from very old peripheral boards.
I think it may be some register data beig write to RAM, and not some bus conflict or RAM corruption. But I may be wrong...


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PostPosted: Mon Feb 29, 2016 2:55 pm 
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Fisher wrote:
Should I add more logic to try to slow M2 down? Maybe add a capacitor?
I don't know :(

You're already using a 74LS part, which effectively has pullup resistors (transistors, really) on all its inputs.

You could try something like
Code:
M2 -|<|-+- 74LSxx input
        |
gnd -C--+
which should delay M2 rising edges but not M2 falling edges

Anyway, Metroid writes to the PRG bank register via $E000, so if there were corruption of PRG RAM it'd be the byte at $6000. But Metroid is also a FDS port, so it writes to $E000 fairly rarely; if you're seeing tile corruption regularly and not just once, it's probably not that. More likely some other PRG RAM issue.


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PostPosted: Mon Feb 29, 2016 6:10 pm 
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Tried the diode and capacitor, no difference.
Tried even a crazy RAM protection circuit made with an LS02:
Attachment:
PRG RAM Proteção NOR.png
PRG RAM Proteção NOR.png [ 1.44 KiB | Viewed 902 times ]

No deal too. :cry:

Let me try to explain exactly where the bug first appears:
I start and go left to get the morph ball, then, go all the way to the right.
The bug starts when I enter the room that I can go up.
At first, the platforms appear fine, when the transitional animation ends some appears a little down, others disappear and are seem just as a solid wall.
I can jump up on the invisible platforms. If I go up, the next screen seems just fine.
About 3 or 4 screens up some parts change from blue to orange.
This is as far as I go in the game, it may or may not have more bugs.
I hope I can do a little video tomorrow, it may show the bugs better.

Would this be CHR RAM related?
The only thing on CHR RAM I see connected on MMC1 is A12. Should I connect it straight to PPU A12?
Again, many thanks for helping. I'm learning a lot while having fun!!


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PostPosted: Mon Feb 29, 2016 6:16 pm 
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... That sounds like mirroring control is broken?


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PostPosted: Mon Feb 29, 2016 6:22 pm 
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The mirroring circuit inside the misterious black bubble?
Can I somehow build a substitute externally like the PRG RAM decoder?
What about CHR RAM? Is the connection to MMC1 CHRA12 correct?


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PostPosted: Mon Feb 29, 2016 6:28 pm 
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Fisher wrote:
The mirroring circuit inside the misterious black bubble?
Yeah, nesdevwiki:MMC#Control.
Quote:
Can I somehow build a substitute externally like the PRG RAM decoder?
Probably not :(

You could try burning a copy of tepples's Holy Diver, Batman! test, and see what it says...

Quote:
What about CHR RAM? Is the connection to MMC1 CHRA12 correct?
Yes.


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PostPosted: Mon Feb 29, 2016 6:40 pm 
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As I have understood, would be necessary to redo almost the entire mapper!!
I really will like to do this, but in the future. My knowledge is still very tiny. :lol:
I should have already made the ROM socketed. I was too confident when I modded it. :roll:

Or, maybe just give up and try a game that don't use the mapper's PRG RAM.
I was thinking in do a translated Megaman 2...
I'll try the Holy Driver tomorrow. I'll post here the results.
Again, many thanks!!
These are by far the best logical circuit classes I have get!!


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PostPosted: Tue Mar 01, 2016 5:00 am 
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Here's the video, some seconds before the first bug:
https://youtu.be/cotiQwsVMRA?t=1m32s

A little before the second bug:
https://youtu.be/cotiQwsVMRA?t=2m55s

The video from the begining, it's boring see me playing Metroid:
https://youtu.be/cotiQwsVMRA

Hope this make easier to get some clues.
Thanks!


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PostPosted: Tue Mar 01, 2016 12:16 pm 
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Yeah, that definitely looks like the mirroring control is broken.

Do traces go between PPU A10, PPU A11, and CIRAM A10 to the black chip-on-board?

( http://wiki.nesdev.com/w/index.php/MMC1_pinout , http://wiki.nesdev.com/w/index.php/Cartridge_connector )


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PostPosted: Tue Mar 01, 2016 1:42 pm 
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Took a look at them.
They're connected according to the schematics I'm following, the same way they're shown on MMC1's pinout.
In fact, I have not touched these pins on my mod.
Looks like it has some internal register bug. :cry:

I had not removed the Flash ROM yet to try the holy driver.
Maybe I don't need to... just disconnect /CE and /OE from one chip and connect to another, making sure all the other pins match.
I think this can save me some time.


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PostPosted: Sun Mar 06, 2016 1:55 pm 
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Holy driver Batman!
Looks like it's trying to comunicate! :shock:
Someone could please tell me what's he's saying?
Attachment:

[ Play Quicktime file ] Voz 010.m4a [ 108.09 KiB | Viewed 801 times ]

Perharps there's some bad soldering somewhere!
Or maybe he just says: "give up you pirate" ? :D


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PostPosted: Sun Mar 06, 2016 2:32 pm 
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The beeps spell out MIR. From the manual:
MIR
The nametable mirroring for this mapper doesn't match any of the supported mappers. Check PA13-PA10, /PA13, CIRAM A10, and CIRAM enable, and don't try running the 78.3 test on an emulator that does not support NES 2.0 format.


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