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PostPosted: Sun Sep 04, 2016 6:43 pm 
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Hello.
I just got an old Super Sprint board and wanted to put some game in.
Pictures:
https://drive.google.com/open?id=0B0OtMD7uFlqgd2xIWmdTLWhFaWc
https://drive.google.com/open?id=0B0OtMD7uFlqgX0VzRUNRUlFpT2c

Since it's totally naked and I don't have the old componnents, I decided to put a nice game on it. :-)
I choose Bisqwit's translation of Castlevania II. Awesome work of him, and even have an option to make it mapper 2 compatible!!
So far, so good. I put an extra little board with an 74HC161 and an 74LS32, wired it up and the game ran just fine.
Pictures:
https://drive.google.com/open?id=0B0OtM ... U1qN3dmYk0
https://drive.google.com/open?id=0B0OtM ... ERqVW5NNzQ

Now, I just wanted to use the save RAM support on it, I got a small 6116 from an old famiclone board.
I was thinking in put the SRAM on the space above the CHR RAM, but I would need to make a nasty rat's nest to plug it on the CPU BUS, so I soldered it under the PRG ROM.
Trying to make things easier, I Plugged the PRG ROM /OE to GND, so I only needed to rewire 3 pins (/CE, /WE and VCC).
I took a look at the wiki, seems that a 4 input NAND is enough to decode the PRG RAM's address. Since I could not find one, I decided to try a 74HC138 I had laying around. This is how I wired it:
Code:
             .-v-.
         M2 -|   |- VCC
    CPU A13 -|   |- NC
    CPU A14 -|   |- NC
        GND -|   |- NC
        GND -|   |- NC
    /ROMSEL -|   |- NC
   SRAM /CE -|   |- NC
        GND -|   |- NC
             `---'

And I tied SRAM's /WE to CPU R/W. For testing I left the battery out, put a 1N4148 diode on the board's VCC and the SRAM VCC like this:
Code:
NES VCC --->|--- SRAM VCC

So far, so good. The game detects the SRAM's presence and allows me to save.
I just save and leave the save screen, when I enter it again, the save is not there anynmore. :roll:

My main doubt is: Did my logic make sense? Should this be working? Since I got the parts from the junk pile there's a big possibility to have got some bad componnent. :-(

Before doing this, I asked the author if a SRAM protection would be needed, he told me that not, and I needed to decode address in $6000-$7FFF range, but $0000-$7FFF is fine and only bit 15 is needed.
Does this mean I can just throw a NAND in /ROMSEL and M2 to do the job?
I have no pictures of how the board is now, but I sure can take some later and post if needed.

Edit: Corrected the naked board's picture, since the were both the same.


Last edited by Fisher on Tue Sep 06, 2016 5:17 pm, edited 1 time in total.

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PostPosted: Sun Sep 04, 2016 8:04 pm 
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Fisher wrote:
but $0000-$7FFF is fine and only bit 15 is needed.
No, it's not the entire range. IIRC, Bisqwit only uses RAM in the range of $6000-$67FF? but that doesn't really simplify your logic at all.

Unfortunately, I don't see anything wrong with what you said you've done so far. Short of having some other program that lets you test the PRG RAM, I don't have any suggestions for next things to try, either.


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PostPosted: Mon Sep 05, 2016 4:17 am 
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Well, I tried Holy Diver Batman!, and it keeps spellig MIR.
I think I have swapped some CHR RAM address pins, could that be inducing this error?
Although I had not played though all the game, besides the saving, it seems to have no other problem.
That doesn't make it free of having some unknown hardware bug. :cry:
Maybe my morse code abilities had not improved at all and it is spelling another thing :-(


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PostPosted: Mon Sep 05, 2016 12:04 pm 
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Holy Diver Batman! indicates 'MIR' when it can't figure out what hardware it's attached to, but UNROM shouldn't be something it has any difficulty with. I'd think?


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PostPosted: Tue Sep 06, 2016 8:54 am 
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Well, I took a look on the address bus, most lines are swapped. :-(

Even if the game seems to be working fine, not passing the HDB tests don't looks good.
I've got some pictures of the actual board, they're a little bad, mostly because of the fluorescent light.
https://drive.google.com/open?id=0B0OtM ... k5TVGNjVjg
https://drive.google.com/open?id=0B0OtM ... 3NpWlEtakE

I'll try the HDB again this when I arrive home, maybe I should record and post the morse code like the last time, since my morse code abilities may be just as poor as before. :?

I have done some tests, and found no shorts or bad connections.
I'll try to talk to Bisqwit, maybe I've just found a bug...


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PostPosted: Tue Sep 06, 2016 12:01 pm 
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Fisher wrote:
Well, I took a look on the address bus, most lines are swapped. :-(
In your original post, you accidentally posted the picture of the obverse of the PCB twice, but even then, I don't see any swapped address lines— "CI-1" is clearly an in-order 28-pin ROM for PRG and J1/J2/J3 can be configured for a 128 KiB 28-pin ROM or smaller, "CI-2" is a 28-pin CHR ROM, "CI-3" is a 24-pin 2 KiB RAM for four-screen nametables (to be used with a 74'00 in the "CI-5" spot), and "CI-4" is for a Namco 108 clone.

In hindsight, that board does rather resemble the board for Gauntlet...

... now that I'm actually looking closely at your board ... what is PRG RAM /CE connected to? I suppose I could write a simple PRG RAM test for you.


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PostPosted: Tue Sep 06, 2016 5:57 pm 
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Sorry for posting the same picture twice, I edited and corrected it.
The swapped address lines are on CHR ROM, wich I changed for a NEC 64s20 SRAM.
If I'm really right, the address lines are swapped this way:
Code:
SRAM     NES
A0  =>   PPU A10 + CIRAM A10
A1  =>   A11
A2  =>   A9
A3  =>   A8
A4  =>   A12
A5  =>   A7
A6  =>   A6
A7  =>   A5
A8  =>   A4
A9  =>   A3
A10 =>   A2
A11 =>   A1

Could this be messing around with the Holy Diver Batman!?

Quote:
In hindsight, that board does rather resemble the board for Gauntlet...

You're right! I Just got a Gauntlet board made by Gradiente, the same manufacturer or this board I have, and they're the same.
Pictures:
https://drive.google.com/open?id=0B0OtM ... UR3UTJiYVE
https://drive.google.com/open?id=0B0OtM ... jRLcVJYOUE

AFAIK, this one I'm modding was Super Sprint, it had the 2kB SRAM and the LS00 unpopulated.
Quote:
... now that I'm actually looking closely at your board ... what is PRG RAM /CE connected to? I suppose I could write a simple PRG RAM test for you.

The PRG RAM /CE is connected to the 74HC138's pin 7. It's impossible to view it on the picture because the wire is passing under the IC (kind of messy wiring, huh?). I would be very glad if you could do the program to me. :lol:

I had no time to try HDB on this board today. A little busier than usual with real life stuff :-)
Maybe tomorrow I can do another try. Last time I tried I've just insulated the HDB's /CE and /OE, tied them together and soldered a small wire to the /ROMSEL. Removed the wire that goes from /ROMSEL to the PRG ROM and had put the HDB's ROM on top of the soldered one, making the pins touch each other, except /CE and /OE.
I think this is the fastest (and maybe the lazyest) way to change the PRG ROM without removing the original chip, is it?


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PostPosted: Tue Sep 06, 2016 11:31 pm 
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Fisher wrote:
The swapped address lines are on CHR ROM, which I changed for a NEC 64s20 SRAM.
(looks at images again)
1- I'm really pretty certain the pins are in order, not scrambled. I mean specifically the "CI-2" one... but honestly everything else looks in order, too...
2- Even if they were scrambled, RAMs don't care. (On a RAM, you can swap address lines in any order; and separately you can swap data lines in any order; because the only data you get out of them is the data you put into them)

Quote:
Could this be messing around with the Holy Diver Batman!?
I doubt it... I mean, Bisqwit's retranslated Castlevania 2 makes extensive use of the CHR RAM, so I can't imagine there's anything wrong there.

Quote:
I would be very glad if you could do the program to me. :lol:
uh, well here's something functional but embarrassing. Probably would have been faster to write it in asm than figuring out how to hammer cc65 back into shape...
Attachment:
ramtest.7z [2.53 KiB]
Downloaded 110 times


Quote:
I think this is the fastest (and maybe the lazyest) way to change the PRG ROM without removing the original chip, is it?
I can't think of anything better ... you are pulling the not-HDB PRG ROM /CE or /OE to +5V when you do this, right?


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PostPosted: Wed Sep 07, 2016 4:59 pm 
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OOPS...
I wasn't tying the onboard's ROM pin to +5V, it was just floating.
Tried this and got the same result, but now, I used an app that decoded the morse code properly.
It's spelling WB, AFAIK it means that the initial bank is wrong.
I have no idea of how to fix this :-(.

I could not try your PRG RAM test program, I'm having trouble with my writter not recognising the flash ROMs I've tried. :cry:
By the way, I just made a little video, in the hope it can help you to have a better idea of what's going on:
https://www.youtube.com/watch?v=TvCxxW8eiO8

Thanks for your support, you're great!!


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PostPosted: Wed Sep 07, 2016 5:40 pm 
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... I think getting WB implies that it thinks it's working with some hardware that isn't UNROM. Which ... well, isn't the most helpful of messages.

Your video indicates that half the saves work? Which makes it seem more suspect that the RAM is damaged than anything else...

Then again, you also managed to crash the game, so it's conceivable there's something else fishy.


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PostPosted: Wed Sep 07, 2016 6:25 pm 
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If you're (say) programming a 64K Holy Diver Batman onto a 128K EPROM (27C010/29F010), you have to program the correct size ROM for the number of unused high address lines that you're grounding. You can't just, say, burn the 128K version and then test it as if it were 64K. That'll give you Wrong Bank for sure.

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PostPosted: Wed Sep 07, 2016 6:52 pm 
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This is the same ROM I used to test that Zelda repro I'm almost giving up.
Just out of curiosity, I socketed the PRG ROM of Life Force and put this same ROM in.
It detected everything just fine.
In fact, I even used it to test some SRAM chips I had laying around.
Old 486's cache RAM chips seem to be great to use as CHR RAM. :wink:
Sadly, HDB doesn't seem to have been designed to test smaller SRAMS, does it?
If it was, I sure have 5 defective 2k SRAMs, including the one I'm using in this project. :-(

Edit: I've found some issues on my writer and fixed it. I just got 2 V29C51002T-90P that are acting weird...
In one of them, I can flash only the first half fine, the rest gives me errors. The other is the opposite, I get errors on the first half and the second checks fine. They may be defective, I think... or, there may be some fancy kind of protection going on. :roll:
Or... the writer have some unfixed problem that I hadn't figured out yet...


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PostPosted: Wed Sep 07, 2016 7:24 pm 
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Holy Diver Batman wasn't designed to test Family BASIC (2K SRAM) or Family BASIC v3 (dual 2K SRAM). But if you can make a board with four sockets for 2K SRAM and a 2-to-4 decoder, you can test all four at once.

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PostPosted: Sat Sep 10, 2016 5:54 pm 
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Well...
Something doesn't seems right...
Holy Diver Batman!! is failing to start, and lidnariq's program is not working either. :roll:
I'm really surprised that the game even runs!!
By the way, I just concatenated Lidnariq's program to create a 128k file and flashed it.
On the test board it made some noises and showed some vertical bars on screen.

Tepples, could you please add support to test 2k SRAM as CHR RAM?
This would make things simplier to me, since I've already made a UxROM test board.
I'm totally out of clues here... no idea on where to start looking for mistakes... :cry:
I had rechecked the wiring many times... seems just fine... I just feel totally blind!!
I mean, the error is right here, under my nose and I just can't find it!!


Last edited by Fisher on Mon Oct 03, 2016 3:12 pm, edited 1 time in total.

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PostPosted: Sat Sep 10, 2016 6:16 pm 
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The noises that it should make is
- an extremely short tone while it clears PPU memory, to human ears it will probably sound like a click
- a short tone at 147Hz while it tests the 2K RAM
- a longer tone at 98Hz if the 2K RAM test passed, while it tests for 8K of RAM
- silence thereafter, but text should appear on-screen

If bars appear on-screen that's ... really weird. Do they all look the same? Or do they feel more random?


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