It is currently Thu Nov 14, 2019 8:14 pm

All times are UTC - 7 hours



Forum rules


1. NO BLATANT PIRACY. This includes reproducing homebrew less than 10 years old, with the exception of free software.
2. No advertising your reproductions, with the exception of free software.
3. Be nice. See RFC 1855 if you aren't sure what this means.



Post new topic Reply to topic  [ 6 posts ] 
Author Message
PostPosted: Wed Feb 13, 2019 11:23 am 
Offline
User avatar

Joined: Tue Sep 06, 2016 4:34 pm
Posts: 55
Location: Evansville, IN
Good day! If you can't tell by my username, I'm a Lupin geek.

I have the original Famicom cart of Lupin Sansei: Pandora no Isan (it's an epoxy cart). I recently purchased a Dragon Slayer IV Famicom donor cart because it has the Namco 108 mapper/protection chip already installed on the cart, and happens to also have the same PRG and CHR sizes as Lupin.

I've downloaded the English translation, stripped the iNES header, split it into the appropriate sized CHR and PRG files. I also have them burned already. For the CHR file, I used an ST M27C512 -- and for the PRG, I used an ST M27C1001.

I've desoldered the original mask ROMs from DS4, and from what I read on the wiki at https://wiki.nesdev.com/w/index.php/Mask_ROM_pinout, I think the 64KiB CHR ROM will be fine as is, but please correct me if I've misunderstood that. Now, on the PRG ROM, since it's a larger 128KiB, my EPROM is a 32-pin chip vs the classic 28-pin mask ROM style. I've made pin reassignments work before, but the question I have is this: it appears that some of the higher address lines A17, A18, and A19 aren't necessarily all accounted for -- where should they be going?

As this ROM uses the 108 Namco chip, some of the PRG address lines are being routed to places where I'm not sure what the actual purpose is... for example, D3 (pin 15) on the 27C1001 would naturally be connecting to pin 8 on the 108 chip.

I know a few of these chips (e.g. 108) haven't been fully analyzed, and I'm prepared to assist anybody with digging deeper into these. I believe I helped Lidnariq a year or two ago with some Nintendo Vs. testing. Ultimately, my goal is to have fun trying to get this project to work and gain more understanding about the hardware.

Pic included to help visualize what I'm working with:
Image

_________________
"Can I keep his head for a souvenir?" -Max


Top
 Profile  
 
PostPosted: Wed Feb 13, 2019 11:54 am 
Offline

Joined: Sun Apr 13, 2008 11:12 am
Posts: 8672
Location: Seattle
Namco 108 only supports 128 KiB PRG and 64 KiB CHR. (There is no PRG A17 and higher)

This PCB expects PRG will be in a JEDEC-standard 28-pin 128 KiB mask ROM. Since you're using a 32-pin 128 KiB UVEPROM, you only need to rewire A16, /ROMOE, and Vcc. If you were using a larger UVEPROM, only then would you need to tie the ROM's extra address lines to something. (For the other end, a mapper with more address lines than the game needs: leave those outputs unconnected)


Top
 Profile  
 
PostPosted: Wed Feb 13, 2019 3:55 pm 
Offline
User avatar

Joined: Tue Sep 06, 2016 4:34 pm
Posts: 55
Location: Evansville, IN
:oops:

Don't I feel embarrassed! I was looking at the wrong datasheet (suppose that's what I get for trying to work on multiple projects at once...) Now that I've pulled up the datasheet again, it's obvious that the highest address line is A16 -- I'm still glad I asked, though, because had I continued on, I probably would have been stuck in that same mindloop for an additional 5-6 hours!

Thanks for adding clarity to my day and for linking to the extra information about the Namcot 108!

_________________
"Can I keep his head for a souvenir?" -Max


Top
 Profile  
 
PostPosted: Wed Feb 13, 2019 4:50 pm 
Offline
User avatar

Joined: Tue Sep 06, 2016 4:34 pm
Posts: 55
Location: Evansville, IN
Follow-up question, though:

On the previously linked wiki, /ROMOE does not appear to be remapped, as in the PRG column, that's where A16 is expected, but /ROMOE isn't remapped anywhere -- I'm assuming it would make sense to just jumper it to /CE in this case, so that its outputs are enabled when the chip is enabled? Or would it be better to jumper it to GND so that it's always enabled?

_________________
"Can I keep his head for a souvenir?" -Max


Top
 Profile  
 
PostPosted: Wed Feb 13, 2019 5:18 pm 
Offline

Joined: Sun Apr 13, 2008 11:12 am
Posts: 8672
Location: Seattle
It is equally safe to connect the EPROM's /OE to ground or to the mapper's /CE output. Either way, it'll work the same way: the ROM will drive the data bus when /CE is low.

(The ROM has two inputs: "Chip enable" and "Output enable". When the chip is enabled, but output is NOT enabled, it consumes more power, but can respond more quickly.)


Top
 Profile  
 
PostPosted: Wed Feb 13, 2019 5:49 pm 
Offline
User avatar

Joined: Tue Sep 06, 2016 4:34 pm
Posts: 55
Location: Evansville, IN
lidnariq wrote:
It is equally safe to connect the EPROM's /OE to ground or to the mapper's /CE output. Either way, it'll work the same way: the ROM will drive the data bus when /CE is low.

(The ROM has two inputs: "Chip enable" and "Output enable". When the chip is enabled, but output is NOT enabled, it consumes more power, but can respond more quickly.)

Thanks for the reply! Before I saw it, I went with my gut and just tied it to GND, since I thought I may be able to avoid any propagation delays between the chip being enabled and having its outputs ready. I'm happy to report that everything is working now, thanks to your responses. 8-)

PIcs attached for posterity.
Image

Image

_________________
"Can I keep his head for a souvenir?" -Max


Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 6 posts ] 

All times are UTC - 7 hours


Who is online

Users browsing this forum: No registered users and 4 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group