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PostPosted: Tue Apr 30, 2019 12:56 pm 
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illuminerdi wrote:
Yeah the other downside of that pic is that I can't see the underside of their add-on PCB which has a bunch of circuit traces on it showing which pins are routed where.
But you don't need to. All ROMs used originally on the SNES used standard footprints, and there's no connections between the OEM PCB and the graft other than the ones you can explicitly see. (BGAs and similar are harder to solder; if you can get away without that why would you bother?) There's even helpful silk on the graft that explains the bits that aren't original connections. (They're labeled ROM-CE, A20, SPC-CE, 21, 23, 22, 20)

The only difference from what I said and what's shown is that I assumed you needed a physically separate ROM to hold the "Expansion" that's mapped to banks $40-$4F, but it RetroCircuits instead used a single ROM that holds both the "Program" and "Expansion", and enables it when either the SPC wants it, or also when the SNES's CPU is trying to access banks $40-$4F.


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PostPosted: Wed May 01, 2019 8:14 am 
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lidnariq wrote:
illuminerdi wrote:
Yeah the other downside of that pic is that I can't see the underside of their add-on PCB which has a bunch of circuit traces on it showing which pins are routed where.
But you don't need to. All ROMs used originally on the SNES used standard footprints, and there's no connections between the OEM PCB and the graft other than the ones you can explicitly see. (BGAs and similar are harder to solder; if you can get away without that why would you bother?) There's even helpful silk on the graft that explains the bits that aren't original connections. (They're labeled ROM-CE, A20, SPC-CE, 21, 23, 22, 20)

The only difference from what I said and what's shown is that I assumed you needed a physically separate ROM to hold the "Expansion" that's mapped to banks $40-$4F, but it RetroCircuits instead used a single ROM that holds both the "Program" and "Expansion", and enables it when either the SPC wants it, or also when the SNES's CPU is trying to access banks $40-$4F.


Yes, I'm aware of the pinouts being standard and easy to connect, however I don't fully understand the expansion circuit that uses the address de/multiplexers (not sure which it uses, can't see them well enough), so I thought that seeing the traces on the underside of the board would help me expedite the process rather than pulling up 10 different data sheets and trying to discern what's going where.


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PostPosted: Wed May 01, 2019 11:21 am 
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No demultiplexers. For whatever reason, the equivalent logic is built out of a 74'00 and 74'32.

As we mentioned in the other thread about demultiplexers / selectors, a demux emits a signal that is "true" (low, in the case of 74'138 and 74'139) when the inputs are correct.

The ROMs also want a signal that is "true"=low to tell them when to emit data to the data bus.

So given the signals SNES A23,22,21,20 and SPC /PRG-CE, the 74'00 and 74'32 calculate the following:
Code:
A23 A22 A21 A20 /PRG-CE  output
 0   1   0   0 don'tcare   0
   don'tcare       0       0
       all others          1


The other parts are the ROM and 3V regulator for the 8MB flash and the three mandatory voltage translation ICs to prevent the SPC from being damaged driving a 3V ROM.


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PostPosted: Thu May 02, 2019 8:52 am 
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lidnariq wrote:
No demultiplexers. For whatever reason, the equivalent logic is built out of a 74'00 and 74'32.

As we mentioned in the other thread about demultiplexers / selectors, a demux emits a signal that is "true" (low, in the case of 74'138 and 74'139) when the inputs are correct.

The ROMs also want a signal that is "true"=low to tell them when to emit data to the data bus.

So given the signals SNES A23,22,21,20 and SPC /PRG-CE, the 74'00 and 74'32 calculate the following:
Code:
A23 A22 A21 A20 /PRG-CE  output
 0   1   0   0 don'tcare   0
   don'tcare       0       0
       all others          1


The other parts are the ROM and 3V regulator for the 8MB flash and the three mandatory voltage translation ICs to prevent the SPC from being damaged driving a 3V ROM.


This is VERY helpful, thank you for breaking that down for me!

So just to make sure I'm understanding you correctly - the 74'00 and 74'32 should output high in every scenario except: 1) when A22 (alone) is low and 2) when /PRG-CE off the SPC7110 is low?

This leads to my next question - when you refer to /PRG-CE, do you know which pin on the SPC7110 corresponds to that signal? According to the pinout at http://www.romhacking.net/documents/%5B398%5DSPC7110F0a.txt there are 3 pins labeled "CE" on the SPC7110 - 47 (/CE), 48 (/OE), and 79 (/RTC-CE). My assumption is that when referring to /PRG-CE you're referring to pin 47 - is that not correct?

I have 5V (UV erasable) EPROMs (27CXXX of all types), so I don't actually need to build a level shift to test this out for myself. Fitting those EPROMs in the same case as the PCB will be tight, but I do know it's possible - I've done it with Star Ocean and SMRPG already, you just have to be willing to shorten the legs of the EEPROMs.

I'll see if I have a 74'00 and 74'32 kicking around in my spare parts, and start work on wiring up a test circuit to test the theory before moving on to designing an PCBs in Eagle.

If I make this work, lidnariq, I'll be happy to send you a translated cart as thanks for helping, if you'd like? I have 3 copies of TMZ in case I fry one testing this theory out. Thank you again for your help with this!


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PostPosted: Thu May 02, 2019 11:30 am 
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illuminerdi wrote:
lidnariq wrote:
Code:
A23 A22 A21 A20 /PRG-CE  output
 0   1   0   0 don'tcare   0
   don'tcare       0       0
       all others          1
1) when A22 (alone) is low
That's not what what I was trying to say... If A23 is low and A22 is high and A21 is low and A20 is low, then the output should be low.
Quote:
My assumption is that when referring to /PRG-CE you're referring to pin 47 - is that not correct?
Seems likely. Certainly "/OE" and "/RTC-CE" are clearly wrong. And the picture of Retrocircuits board showed just picking up the signal from some random via.

Quote:
I have 5V (UV erasable) EPROMs (27CXXX of all types)
Do those come in 8MiB (4 Mi x 16bit)? Otherwise, you'll need to handle the 5MiB "data" ROM with multiple ROMs.

Quote:
If I make this work, lidnariq, I'll be happy to send you a translated cart as thanks for helping, if you'd like?
I appreciate the offer, but I just haven't been able to make myself sit down in front of the old SNES for several years now.


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PostPosted: Thu May 02, 2019 12:43 pm 
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lidnariq wrote:
That's not what what I was trying to say... If A23 is low and A22 is high and A21 is low and A20 is low, then the output should be low.


I see what you mean - I'll need to run wires off of A23+A22+A21+A20 so that when all 4 line up to the scenario you listed, THEN set the output to low for that chip. It looks like that's what the retrocircuits board already does for one of the logic checks.

It seems to me that there are 2 separate logic circuits of 2 chips on the Retrocircuits board - your previous post was unclear - am I going to need 2 pairs of 74LS00+74LS32? I can figure it out on my own, I just don't understand logic gate chips well enough yet to understand whether or not I'm looking at separate logic circuits or if I can handle all the logic circuits necessary with a single pair of those chips or not. I've used Logic Gates before, but that was in pre-fab repro boards where I didn't actually understand HOW they worked, just that the board said to solder a 74LS32 to a certain point in order to make it work, so I dutifully did so...and it worked.

I pulled the datasheets - the 74LS00 is a NAND gate and the 74LS39 is an OR gate, so I'll need to figure out the exact logic and how to line it up correctly, but I think I can manage - feel free to provide any suggestions or clarifications if you know off the top of your head how this works better than I do.

illuminerdi']My assumption is that when referring to /PRG-CE you're referring to pin 47 - is that not correct?[/quote]
[quote="lidnariq wrote:
Seems likely. Certainly "/OE" and "/RTC-CE" are clearly wrong. And the picture of Retrocircuits board showed just picking up the signal from some random via.


Ok so Pin 79 (RTC-CE) of the SPC7110 does have a jumper between one of its test points and the Retrocircuits pad labeled SPC-CE, so it does look like at least one of the logic circuits is reading for scenarios when /RTC-CE is pulled low.

There's 2 other taps on the Retrocircuits board - one says ROM-CE and one says A20 - and they're going to the 8M EEPROM - any idea how they fit in? I'm assuming that it's reading when the ROM /CE is pulled low and when /A20 is pulled low, which makes me think that I should modify your original suggestion so that instead of just reading /PRG-CE to be low it should look as follows:

Code:
RTC-CE  A20  ROM-CE   output
   0      0      0      0


lignariq wrote:
Do those come in 8MiB (4 Mi x 16bit)? Otherwise, you'll need to handle the 5MiB "data" ROM with multiple ROMs.


Yes, the M27C800 is an 8MiB 5V EPROM that can be organized as either 1M word x 8-bit or 512K word x 16-bit - http://noel.feld.cvut.cz/hw/st/4630.pdf, so I believe it is a suitable drop-in replacement for this. I can just pad the actual ROM to 8MiB when programming it since those areas of memory just won't be called ever by the game code.


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PostPosted: Thu May 02, 2019 1:01 pm 
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illuminerdi wrote:
It seems to me that there are 2 separate logic circuits of 2 chips on the Retrocircuits board - your previous post was unclear - am I going to need 2 pairs of 74LS00+74LS32?
No, I don't think so. I saw only the following chips:
1 16 megabit (2 Megabyte, 2 Mi x 8b) 5V flash
3 voltage translation ICs, part number unknown, all in 20-pin TSSOPs
1 3V regulator in SOT-23
1 64 megabit (8 Megabyte, 4 Mi x 16b) 3V flash
1 74'32
1 74'00

Quote:
I've used Logic Gates before, but that was in pre-fab repro boards where I didn't actually understand HOW they worked
So you understand the concept of logical OR, right?
If this OR that is true, then the result is true? because either this or that or both could be true?
This is the same idea. A 74'32 emits a signal that is high ("true") when either of its inputs are high ("true").
A 74'00 (NAND = AND followed by NOT) emits a signal that is low when both of its inputs are high ("true").

illuminerdi wrote:
Ok so Pin 79 (RTC-CE) of the SPC7110 does have a jumper between one of its test points and the Retrocircuits pad labeled SPC-CE,
You're misreading the picture. The silkscreen labeled "SPC-CE" connects to a via, not pin 79.

Quote:
There's 2 other taps on the Retrocircuits board - one says ROM-CE and one says A20 - and they're going to the 8M EEPROM - any idea how they fit in?
Best guess: ROM-CE is the signal that tells the "program and expansion" ROM to be enabled, and is the result of the pile of logic. "A20" is probably SNES A22. Both conceptually flow from the right graft PCB (where they're generated) to the left graft PCB (where they're used)

Quote:
your original suggestion so that instead of just reading /PRG-CE to be low it should look as follows
There are only two correct tables:
One involves two ROM ("program and expansion" and "data") and for that the table I gave you is the only correct one.

If using three ROMs (one each for "program", "expansion" and "data"), then you don't need to modify "SPC-CE".

Quote:
Yes, the M27C800 is an 8MiB 5V EPROM that can be organized as either 1M word x 8-bit or 512K word x 16-bit
That is an 8 megabit 'PROM, not an 8 megabyte. You need 40 megabits (or more) of storage to hold the expanded "data" ROM.


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PostPosted: Thu May 02, 2019 4:11 pm 
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lidnariq wrote:
No, I don't think so. I saw only the following chips:
1 16 megabit (2 Megabyte, 2 Mi x 8b) 5V flash
3 voltage translation ICs, part number unknown, all in 20-pin TSSOPs
1 3V regulator in SOT-23
1 64 megabit (8 Megabyte, 4 Mi x 16b) 3V flash
1 74'32
1 74'00


I didn't realize there was such a thing as ICs for level shifting - I thought that was pretty much done exclusively via diodes/resistors/caps. Also a circuit I've never built...

lidnariq wrote:
So you understand the concept of logical OR, right?
If this OR that is true, then the result is true? because either this or that or both could be true?
This is the same idea. A 74'32 emits a signal that is high ("true") when either of its inputs are high ("true").
A 74'00 (NAND = AND followed by NOT) emits a signal that is low when both of its inputs are high ("true").


Thanks for the explanation - obviously I'm familiar with OR and I've seen NAND before though I didn't know offhand how it worked since it's not something that comes up a lot in the software development world (and my programming skills are limited, I mostly write scripts and tools for my office, I'm not a "developer").

lidnariq wrote:
You're misreading the picture. The silkscreen labeled "SPC-CE" connects to a via, not pin 79.


Yeah it looked kind of like it was connect to pin 79 but you are indeed correct - I checked it against an unmodified board picture and it's a via going somewhere. I'll take a look when I get home tonight as to where that via actually connects to. I could probably find out now but I'm at work and it's hard enough to find decent quality pics of the even the front of the PCB...


lidnariq wrote:
One involves two ROM ("program and expansion" and "data") and for that the table I gave you is the only correct one.


Ok, thanks for clarifying that for me. I was making incorrect assumptions due to my lack of knowledge regarding level shifting ICs. TIL. Knowing how the logic works is a major step here, I can kludge/learn how to build a proper logic circuit.

lidnariq wrote:
That is an 8 megabit 'PROM, not an 8 megabyte. You need 40 megabits (or more) of storage to hold the expanded "data" ROM.


Yeah I wasn't paying close attention, sorry for being dense, I do actually know the difference between the two, honest! You are correct, a 5MB rom file would be 40Mbits and thus require an EPROM that was at least 64Mbit.

THAT is going to be much harder to fix. I found a few vague mentions in various places for 5V 64Mbit 4Mb x 16 EPROMs (the M27C642 / M27C640) but I could not find a single listing for one for sale ANYWHERE. I'm guessing they were pretty rare back in their day and there aren't many/any still hanging around these days. Or they never made it to production.

So that leaves me with 2 choices - I can either obtain a 64M 3V EEPROM and build a level shifting circuit, OR I can go the route you previously mentioned of splitting it into 3 ROMs.

Ok so...this is starting to make sense but still doesn't fully fit in my head. I still don't get what the logic circuit is doing, exactly. As best as I can tell, since the Expansion ROM data lives in bank $40, the code is somehow accessing the contents of $40 without lighting up A22. Via the SPC7110? Then, when the game lights up A22 it means that a piece of code is trying to access the data that originally lived at $40 (on a stock ROM), so now it's time to bankswitch the contents of $40 and $50?

In the SPC7110 schematics that I read, it indicated that decompressed data from the SPC7110 originally lived at $50-$5F. I'm not seeing anything in the memory map that indicates that data was remapped somewhere else, or is that irrelevant since a call to $50 would route "normally" and not be translated to whatever ROM banks that would otherwise correspond to $50, since technically that address isn't accessible even in an ExHiROM game and is instead handled via bankswitching between 2 32Mbit chips instead?

Am I understanding this correctly or am I still off target. I'm getting closer, I think once I get the board in front of me and can start referencing back and forth I'll have a better idea of what I'm looking at. Thanks again.


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PostPosted: Thu May 02, 2019 4:33 pm 
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illuminerdi wrote:
As best as I can tell, since the Expansion ROM data lives in bank $40, the code is somehow accessing the contents of $40 without lighting up A22. Via the SPC7110?
Apparently the "program" ROM doesn't go via the SPC7110 at all, and is just mapped statically (by the SPC7110) in banks $00-$0F, $80-$8F, and $C0-$CF.

Quote:
Then, when the game lights up A22 it means that a piece of code is trying to access the data that originally lived at $40 (on a stock ROM), so now it's time to bankswitch the contents of $40 and $50?
Not really bankswitching? The SNES's CPU does have a concept of "bank", but it's just literally part of the address bus, not separate state. Nothing like smaller CPUs that can only natively handle 64 KiB.

Quote:
is that irrelevant since a call to $50 would route "normally" and not be translated to whatever ROM banks that would otherwise correspond to $50
Correct, with the SPC7110, banks $40-7D don't directly map to ROM. Banks $40-$4F are completely unused, banks $50-$5F are used for this decompression interface, and ... I don't know what's in $60-7D. Probably just the battery-backed RAM.

Quote:
since technically that address isn't accessible even in an ExHiROM game and is instead handled via bankswitching between 2 32Mbit chips instead?
However, that's wrong. That's the only place that a mode $25 (pirates call it "exhirom") game can access the entirety of its 6th megabyte of ROM contents.


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