(SNES)Help With Circuit for LoRom M27C322

[LittleRain]

I ordered some IC's to make some SMW Rom hack carts, but I'm a little confused with some parts of the circuit. (I'm making my own PCB's)
Here are the parts I'm using, and I'll put my issues below.
Also, if someone is willing to help me out on skype, I will send you a board or 2 (as long as shipping isn't ridiculous).


EPROM - 27C322 x1 (32Mb, 16-bit)
SRAM - gm76c88al-15 x1 (8k, or 16k? "It says 65,536 bit, which is 8k, but also says 8,192 words, which is 16k" )
Multiplexer - 74HC257 x2
Decoder - 74HC139 x1
As well as Passives and battery

Problem 1!:
This is what matters the most.
The EPROM I use requires a couple multiplexers since it has a 16-bit output, I hooked them up but I still don't understand how I am going to make use of the full 32 Mbs, since A0 is now being used for the multiplexer input.
And I really need the full 32Mb (4MB) for the ROM hacks, specifically Invictus, and Super DGR World.
I just opened Invictus in a HEX Editor and there is tons of blank values, I assume its something to do with memory mapping.

So how do I access the full 32Mb/4MB with A0 going to my multiplexers?

Also, does the current decoder setup allow me to use the full EPROM?
I included my schematic at the bottom.

Problem 2:
On the Original SMW cart..
Are they diodes zener diodes, or regular diodes? They look like Zener diodes, but they are old parts so I'm not sure.
And is mine a repo, because it uses a 74hc139 instead of the MAD?

Problem 3:
My SRAM chip has 2 chip select pins, one is active low, and the other active high. Are both necessary? Because if I could use the active high, I could remove Q1.

Problem 4:
What pin on the ROM (MX23C4001-12 on the SMW Cart, not my EPROM) is connected to the 1Y0 Decoder pin? When I check with my multi meter its going to pin 31 on the ROM, and some datasheets are saying its A18, and others are saying its A9)
I thought it was supposed to go to the ROM's /OE pin?
This page shows write enable, should I assume the datasheet for those chips are wrong? I couldn't find the MX datasheet, only X23C4000, UMC23C4000/1 and PD23C4001E

Problem 5:
Some Pinouts online say BA5 (pin46) on LoRom is A20, and others say its A21.
Same thing with BA6, some say its A21, some say its A22.
I'm going to assume its the former for both pins, but just want to make sure.


Here is my schematic. I know some of my address lines are wrong. And I'm not sure if the decoder setup allows for full use of the EPROM.
https://i.postimg.cc/JhybGvsM/32-Mb-Lo- ... ematic.png

[poorstudenthobbyist]

Problem 1!:
This is what matters the most.
The EPROM I use requires a couple multiplexers since it has a 16-bit output, I hooked them up but I still don't understand how I am going to make use of the full 32 Mbs, since A0 is now being used for the multiplexer input.
And I really need the full 32Mb (4MB) for the ROM hacks, specifically Invictus, and Super DGR World.

I have details on this on my website - scroll down to the section on how this adapter board works, it'll show you the correct wiring and explanation:
https://thepoorstudenthobbyist.com/2019 ... ter-board/

Problem 2:
On the Original SMW cart..
Are they diodes zener diodes, or regular diodes? They look like Zener diodes, but they are old parts so I'm not sure.

These are regular ol' diodes, not Zeners. You could probably use Schottky diodes if you wanted to, but I use 1N914s without problems.

And is mine a repo, because it uses a 74hc139 instead of the MAD?

Some older LoROM boards use the '139's, the MAD-1 chips came later. I've never seen a HiROM board with '139's, but they could be out there.

Problem 3:
My SRAM chip has 2 chip select pins, one is active low, and the other active high. Are both necessary? Because if I could use the active high, I could remove Q1.

The answer to this is considerably long, but the quick and easy answer is yes, you need both. The long answer includes a lot of analysis of standby current draw of the SRAM chip and stuff... it's on my website too. The circuit is included. Read the SRAM and the battery section.

https://thepoorstudenthobbyist.com/2019 ... tion/#sram

Problem 4:
What pin on the ROM (MX23C4001-12 on the SMW Cart, not my EPROM) is connected to the 1Y0 Decoder pin? When I check with my multi meter its going to pin 31 on the ROM, and some datasheets are saying its A18, and others are saying its A9)
I thought it was supposed to go to the ROM's /OE pin?

Problem 5:
Some Pinouts online say BA5 (pin46) on LoRom is A20, and others say its A21.
Same thing with BA6, some say its A21, some say its A22.

You can find the answers to these questions on this page under the LoROM memory map explanation:

https://thepoorstudenthobbyist.com/2019 ... ion/#lorom

There are a few ways you can wire the decoder up based on what your inputs are, but the schematic I use is on that page.
And LoROM boards skip A15, so BA5 is connected to EPROM A20 on LoROM carts, BA6 is connected to EPROM A21.

I don't have time to check your schematic for accuracy, but this info should help you on your way

[lidnariq]

SRAM - gm76c88al-15 x1 (8k, or 16k? "It says 65,536 bit, which is 8k, but also says 8,192 words, which is 16k" )

"word" doesn't specify anything about the width of those words. The datasheet says it's 8192 words by 8 bits, which is 65536 bits, accessible as 8192 octets.

One can purchase RAMs that are wider or narrower than 8 bits, although most of the narrower ones are no longer manufactured.

since A0 is now being used for the multiplexer input.

Exactly.

The 27C322 holds its data as 2097152 words by 16 bits. In order to convert this into the 8-bit-wide bus needed by the SNES, the multiplexer uses a signal from the SNES to do this. The easiest option is to use A0, because then the data in the ROM is the same order as in the file on your disk. (When A0 is low, they pick one half of the 16-bit data bus. When A0 is high, they pick the other half).

Are they diodes zener diodes, or regular diodes? They look like Zener diodes, but they are old parts so I'm not sure.

They're regular diodes.

And is mine a repo, because it uses a 74hc139 instead of the MAD?

No. Most of Nintendo's early carts used 74'139s instead of custom silicon. The last letter of the PCB name (e.g. "1A3B") specifies what hardware is on the cart. (nocash's FullSNES § SNES Cartridge PCBs)

I've never seen a HiROM board with '139's, but they could be out there.

1J3B

My SRAM chip has 2 chip select pins, one is active low, and the other active high. Are both necessary? Because if I could use the active high, I could remove Q1.

Yes, that's fine. Feel free to use /CS to enable the RAM by decoding logic, and +CS for protection.

[schematic]

You can leave /IRQ floating.
Do not connect /SNESRD to /ROMCE and /CART to /ROMOE: this is slower and higher power. Instead, /CART and other address lines should always connect to /ROMCE and /SNESRD should connect directly to /ROMOE.
Do not connect 74'257's /OE to ground. That means they're always driving the SNES's data bus, which means that the SNES's CPU can't.
Address lines on the 27'322 are numbered in terms of 16-bit words. (If all higher address lines are low), A0 specifies whether you're addressing the first or second 16-bit word of ROM. But that's not useful to use these in the context of the SNES, which needs 8-bit words. Each address line needs to be used once, and exactly once: if it's connected multiple times it reduces the total amount of memory that can be addressed.

[poorstudenthobbyist]

My SRAM chip has 2 chip select pins, one is active low, and the other active high. Are both necessary? Because if I could use the active high, I could remove Q1.

Yes, that's fine. Feel free to use /CS to enable the RAM by decoding logic, and +CS for protection.

This would let the game work, but the SRAM won't be put into a low-leakage state when power is off. This sucks the battery power more than it should.
https://forums.nesdev.com/viewtopic.php ... 0&start=30

[lidnariq]

Yeah, but that design was trying to deal with RAMs with a single /CE input. With two separate enables, one of which is positive sense, it's easier to get the 0V necessary to put it into deep power-saving mode.

Might even be sufficient to just connect /RESET to +CE, although I guess we'd still want a ≈1MΩ pulldown on the pin.

[LittleRain]

Thanks for your time guys. It takes a lot of work to quote multiple questions haha.

I have details on this on my website - scroll down to the section on how this adapter board works, it'll show you the correct wiring and explanation:
https://thepoorstudenthobbyist.com/2019 ... ter-board/

Thanks, I did not realize there was more info on the subject other than the main tutorial.

These are regular ol' diodes, not Zeners. You could probably use Schottky diodes if you wanted to, but I use 1N914s without problems.

They're regular diodes.

OK good to clarify.

Some older LoROM boards use the '139's, the MAD-1 chips came later. I've never seen a HiROM board with '139's, but they could be out there.

No. Most of Nintendo's early carts used 74'139s instead of custom silicon. The last letter of the PCB name (e.g. "1A3B") specifies what hardware is on the cart. (nocash's FullSNES § SNES Cartridge PCBs)

Ah ok. Yeah I have kept seeing people mention the MAD-1, so I was confused to see a 74hc139 on my board.

The model number on mine is 1A1B, and it seems to be from 1990.

The answer to this is considerably long, but the quick and easy answer is yes, you need both. The long answer includes a lot of analysis of standby current draw of the SRAM chip and stuff... it's on my website too. The circuit is included. Read the SRAM and the battery section.

https://thepoorstudenthobbyist.com/2019 ... tion/#sram

Ah thank you.
I'm going to do it a bit differently, I posted in the NPN thread you posted below, will report my power draw when I finally get it in.

You can find the answers to these questions on this page under the LoROM memory map explanation:

https://thepoorstudenthobbyist.com/2019 ... ion/#lorom

There are a few ways you can wire the decoder up based on what your inputs are, but the schematic I use is on that page.
And LoROM boards skip A15, so BA5 is connected to EPROM A20 on LoROM carts, BA6 is connected to EPROM A21.

I don't have time to check your schematic for accuracy, but this info should help you on your way

As for problem 4, I wasn't very clear, but it was a question about the SRAM on the SMW cartridge.
All the datasheets were conflicting with eachother, but yeah I guess it doesn't matter, as long as I know which pin its supposed to go to.


Ok I understand why I got that confused.
I was looking up the pinout for the edge card on google images, and instead of presenting the pin names for the actual card's pins, they presented what its connected to.

But about the decoder, I wasn't confused before reading that but now I am.
Specifically the part about how you wired the decoder is confusing me.

You have 1A and 1B connected to A15, where i had them connected to A21 and A22.
For the SWM cart its A18/A19.
And then your ROMOE 1Y3, and mine is 1Y0.
You state there are many ways to hook up the decoder for LoRom and get the same results.
I still don't fully understand, but I might have an idea.

Please correct me if I'm wrong, but the only way these 3 setups would all enable the EPROM is this...

When ever the CPU is trying to access the EPROM, A15 will always be high, and A18(BA2) to A22(BA6) will always be low?

But then, wouldn't A15 always being high severely affect what addresses are being targeted on the EPROM?

Nevermind, I did not realize that A15 is not connected to the EPROM.

"word" doesn't specify anything about the width of those words. The datasheet says it's 8192 words by 8 bits, which is 65536 bits, accessible as 8192 octets.

One can purchase RAMs that are wider or narrower than 8 bits, although most of the narrower ones are no longer manufactured.

Word is pretty standard for 2 bytes now a days.

Exactly.

The 27C322 holds its data as 2097152 words by 16 bits. In order to convert this into the 8-bit-wide bus needed by the SNES, the multiplexer uses a signal from the SNES to do this. The easiest option is to use A0, because then the data in the ROM is the same order as in the file on your disk. (When A0 is low, they pick one half of the 16-bit data bus. When A0 is high, they pick the other half).

Ya I had that part figured out, and I kind of thought shifting A1 to A0 of the EPROM was the right thing to do, but just wanted to make sure.
On my schematic I attached A0 to A20 on the EPROM before I added in the multiplexers, and for the sake of uploading the image I tied A0 on the EPROM to ground to atleast show I knew A0 wasn't supposed to go to A0 on the EPROM.
I also read a week prior that there were other pins being used differently for LoRom (turned out to be A15+), so I also had to ask anyways because I was having trouble finding the info online.

Yes, that's fine. Feel free to use /CS to enable the RAM by decoding logic, and +CS for protection.

After reading the PoorStudent's page about battery usage I decided to keep Q1, but instead of using his circuit, I modified Nintendo's to work with the 2 CS pins.

You can leave /IRQ floating.
Do not connect /SNESRD to /ROMCE and /CART to /ROMOE: this is slower and higher power. Instead, /CART and other address lines should always connect to /ROMCE and /SNESRD should connect directly to /ROMOE.
Do not connect 74'257's /OE to ground. That means they're always driving the SNES's data bus, which means that the SNES's CPU can't.
Address lines on the 27'322 are numbered in terms of 16-bit words. (If all higher address lines are low), A0 specifies whether you're addressing the first or second 16-bit word of ROM. But that's not useful to use these in the context of the SNES, which needs 8-bit words. Each address line needs to be used once, and exactly once: if it's connected multiple times it reduces the total amount of memory that can be addressed.

I decided to tie /IRQ high with a 10k resistor.

So wait, the /RD(23) pin should be connected to /ROMOE from the 139, or the EPROM /OE-VPP pin?
And /CART should be connected to the EPROM's /CE pin?
Just checking with the PoorStudent's page again, he says /OE-VPP should always be connected to ground. And the EPROM's /CE pin should be connected to the output of the 139.

Other than that I fixed everything else.

Here is my new schematic, I think I'm ready to order (after I route the board of course).

[lidnariq]

Word is pretty standard for 2 bytes now a days.

Dates to the 8086 and 68k, where WORD was appropriated in programmer's parlance for the native data bus width of the machine. (Hence why "DWORD" and "QWORD" mean 32-bit and 64-bit). But in a hardware context, a word is just the output width of the hardware. Modern DRAM ICs often have a native word size of 32, 36, 64, or 128 bits. More-or-less every CPU newer than the 286 and 68k have a word size that's 32 bits, or (more increasingly) 64.

[LittleRain]

Word is pretty standard for 2 bytes now a days.

Dates to the 8086 and 68k, where WORD was appropriated in programmer's parlance for the native data bus width of the machine. (Hence why "DWORD" and "QWORD" mean 32-bit and 64-bit). But in a hardware context, a word is just the output width of the hardware. Modern DRAM ICs often have a native word size of 32, 36, 64, or 128 bits. More-or-less every CPU newer than the 286 and 68k have a word size that's 32 bits, or (more increasingly) 64.

Ah very interesting. I just looked into it more and found out Dword stand for Double, and Qword stands for quad.


I routed my board, and I think its all good to go. Wish me luck!

[tepples]

On the one hand, DWORD as 32 bits and QWORD as 64 bits were named when Windows was running on 8088 and 286 processors. Because this was long before 1999, the C99 standard names uint32_t and uint64_t respectively weren't invented yet.

On the other hand, DWORD also happens to be enough bits to hold the ASCII codes for the word "DAMN", which is called "the D-word" by moms trying to keep their single-digit-year-old children's vocabulary G rated.

[nocash]

80x86 language also has the FWORD, and the PWORD (and, yes, I know what they mean in adult language, they are for sex bytes). But, what is that QWORD?

[lidnariq]

QWORDs are for holding 8087 doubles. TBYTEs are for holding 8087 long doubles.
—

So wait, the /RD(23) pin should be connected to /ROMOE from the 139, or the EPROM /OE-VPP pin?
And /CART should be connected to the EPROM's /CE pin?

The '257s make things a little different here. I'm going to first pretend you have a cart that doesn't need the '257s, and then get back to what the '257s are doing.

The two signals to the ROM mean two things:
* /CE means "start consuming power and start looking up data inside the ROM"
* /OE means "drive the value you found onto the data bus"

A bare SNES cart with no RAM has the simplest thing going on: /ROMSEL=/CART=pin49 should be connected to ROM /CE, and /RD=23 should be connected to ROM /OE. This is for power and speed reasons: all ROMs consume power when their /CE input is enabled and respond faster. If you look at any ROM's data sheet, it specifies both a time from /CE driven low (or address changed) to output data valid, and a time from /OE driven low to output data valid. So for speed reasons, you want to tell the ROM to start looking up the data as soon as you have enough information to do this.

In the SNES, /ROMSEL=/CART=pin49 changes at the same time the address bus does. /RD changes later, and says that the SNES's CPU wants something to drive the data bus.

A SNES cart with RAM has to additionally divide memory regions for the ROM and for the RAM. This is what the 74'139 and/or MAD-1 are doing. They ultimately should still control the ROM's /CE input for the same reason: the sooner the ROM knows where it should be looking for data, the faster it can respond.

The '257s throw a wrench into this. Because they completely separate the ROM's data bus from the SNES's data bus, the ROM can do whatever, and it's more-or-less fine. (For power reasons you may still want to connect ROM /CE to the output from the 74'139 ... but you can also get away with not caring and just grounding it. The downside is just some extra heat in the ROM and the SNES's power regulator. And ROM /OE is similarly irrelevant, as long as it also is low when the SNES asks for data out of the ROM.). However, now the '257s should only drive the data bus at the correct time: when told to by both the output from the 74'139 and the /RD signal. If they drive at other times, the '257s will get in a fight with the PPU, with the SNES's RAM, with the cart's RAM, &c.

Note that this applies only to using a 74'257. If you instead use a 74'3257, that part is an analog multiplexer, and you can (and probably should) use the ROM's /CE and /OE outputs as originally intended.

Subsequent experimentation has found that you can mostly get away with connecting the '257s /OE to the /CE signal from the 74'139 : if it's at the correct address the game won't choose to try to write to ROM (nothing would happen), and the brief moments at the beginning and end of each access cycle, where the address bus is changing, are brief enough to probably be safe.

[schematic]

You corrected most of the ROM pins, but you missed SNESA8 to ROMA8.

I'd personally rename your "ROMOE" signal to "ROMCE", because semantically it's the signal that decodes addresses (and thus "which Chip should be Enabled" instead of "when the ROM's Output should be Enabled"), but as stated, that's semantics, not functionally wrong.

If you want, I ported the SuperCIC code to a smaller cheaper PIC.

I'm uncomfortable having the diode from cartVcc to /RESET. You really want to wait for the SNES to pull the signal up, after the CIC and everything else has started permitting things to run. That said, maybe you intended to have the diode point the other direction? So that /RESET can't be higher than cartVcc when power is removed.

[LittleRain]

Just a warning to anyone using my circuit for reference, the battery circuit, specifically at Q1 does not work for all chips.
I tested it on a breadboard with a flash chip before I ordered my boards and it worked, but its not working with my SRAM chip, the GM76C88AL does not let you sink current from /CS1.
For now my carts will have to make due without a battery, they are way too thick anyways, and some SOP packages I received were not the same width as I was expecting, so its not a big deal.

On the one hand, DWORD as 32 bits and QWORD as 64 bits were named when Windows was running on 8088 and 286 processors. Because this was long before 1999, the C99 standard names uint32_t and uint64_t respectively weren't invented yet.

On the other hand, DWORD also happens to be enough bits to hold the ASCII codes for the word "DAMN", which is called "the D-word" by moms trying to keep their single-digit-year-old children's vocabulary G rated.

Ahh haha, very interesting.

QWORDs are for holding 8087 doubles. TBYTEs are for holding 8087 long doubles.
—

So wait, the /RD(23) pin should be connected to /ROMOE from the 139, or the EPROM /OE-VPP pin?
And /CART should be connected to the EPROM's /CE pin?

The '257s make things a little different here. I'm going to first pretend you have a cart that doesn't need the '257s, and then get back to what the '257s are doing.

The two signals to the ROM mean two things:
* /CE means "start consuming power and start looking up data inside the ROM"
* /OE means "drive the value you found onto the data bus"

A bare SNES cart with no RAM has the simplest thing going on: /ROMSEL=/CART=pin49 should be connected to ROM /CE, and /RD=23 should be connected to ROM /OE. This is for power and speed reasons: all ROMs consume power when their /CE input is enabled and respond faster. If you look at any ROM's data sheet, it specifies both a time from /CE driven low (or address changed) to output data valid, and a time from /OE driven low to output data valid. So for speed reasons, you want to tell the ROM to start looking up the data as soon as you have enough information to do this.

In the SNES, /ROMSEL=/CART=pin49 changes at the same time the address bus does. /RD changes later, and says that the SNES's CPU wants something to drive the data bus.

A SNES cart with RAM has to additionally divide memory regions for the ROM and for the RAM. This is what the 74'139 and/or MAD-1 are doing. They ultimately should still control the ROM's /CE input for the same reason: the sooner the ROM knows where it should be looking for data, the faster it can respond.

The '257s throw a wrench into this. Because they completely separate the ROM's data bus from the SNES's data bus, the ROM can do whatever, and it's more-or-less fine. (For power reasons you may still want to connect ROM /CE to the output from the 74'139 ... but you can also get away with not caring and just grounding it. The downside is just some extra heat in the ROM and the SNES's power regulator. And ROM /OE is similarly irrelevant, as long as it also is low when the SNES asks for data out of the ROM.). However, now the '257s should only drive the data bus at the correct time: when told to by both the output from the 74'139 and the /RD signal. If they drive at other times, the '257s will get in a fight with the PPU, with the SNES's RAM, with the cart's RAM, &c.

Note that this applies only to using a 74'257. If you instead use a 74'3257, that part is an analog multiplexer, and you can (and probably should) use the ROM's /CE and /OE outputs as originally intended.

Subsequent experimentation has found that you can mostly get away with connecting the '257s /OE to the /CE signal from the 74'139 : if it's at the correct address the game won't choose to try to write to ROM (nothing would happen), and the brief moments at the beginning and end of each access cycle, where the address bus is changing, are brief enough to probably be safe.

[schematic]

You corrected most of the ROM pins, but you missed SNESA8 to ROMA8.

I'd personally rename your "ROMOE" signal to "ROMCE", because semantically it's the signal that decodes addresses (and thus "which Chip should be Enabled" instead of "when the ROM's Output should be Enabled"), but as stated, that's semantics, not functionally wrong.

If you want, I ported the SuperCIC code to a smaller cheaper PIC.

I'm uncomfortable having the diode from cartVcc to /RESET. You really want to wait for the SNES to pull the signal up, after the CIC and everything else has started permitting things to run. That said, maybe you intended to have the diode point the other direction? So that /RESET can't be higher than cartVcc when power is removed.

Yeah I know about OE and CE, been making circuits for a while before this.

Is there actually carts with no RAM? Does the SNES have internal memory?

I did eventually fully understand what was going on with the 129 and 257, thepoorstudent had a picture of a memory map, and then it all made sense.

You are right I should change the name, I was using that trace with the !OE!/VPP before, and just forgot to swap it.


And oh man you saved me, I was uploading the Supercic code from the sd2snes website wondering why it wasn't working. Everyone in the comment section was mentioning the 629 so I thought they shared the same binary.
I even went the lengths to simulating it in MPLAB, it actually was half working, though one of the CICOUT signals wasn't being produced, or maybe it was CICIN cant remember. For USB devices IN means OUT from the device perspective. If I remember correctly, I was sending a clock signal to CLK, and a randomish signal to CICIN, which produced results on CICOUT1 or CICOUT2.

I ended up having to take the original cic from a SMW cart, and I was finally able to get it going, now I can put that back in the cart.

Edit: Oh you ported it to something smaller than the 629... I should have read further. I wonder why my 629 supercic chips aren't working... Possibly because I didn't use a pullup resistor is my best guess.

[lidnariq]

Is there actually carts with no RAM? Does the SNES have internal memory?

There are a significant number. Any cart PCB code that ends with "0N" has neither RAM nor battery, such as:
1A0N: rev -01 -02 -10 -20 -30
2A0N: rev -01 -10 -11 -20 (YA0N-01)
BA0N: rev -01 -10 -SP1
1B0N: rev -01 -02 -03 -10 (1K0N-01)
1J0N: rev -01 -10 -20
2J0N: rev -01 -10 -11 -20 (YJ0N-01 3J0N-01)
BJ0N: rev -01 -10 -20

The SNES provides no save memory; the cost of an additional IC just to hold a save was often deemed not worth the cost, and games either were designed to be played through in one sitting, or used passwords. (It does provide 128KB of DRAM while the game is running)

[LittleRain]

There are a significant number. Any cart PCB code that ends with "0N" has neither RAM nor battery, such as:

The SNES provides no save memory; the cost of an additional IC just to hold a save was often deemed not worth the cost, and games either were designed to be played through in one sitting, or used passwords. (It does provide 128KB of DRAM while the game is running)

Ahhh, I did not realize the SRAM is only used for saving. I was under the impression that cartridges supplied their own RAM, saving or not.


Oh and I almost forgot pictures.

I was going to add you to the thank you, but it was getting too long.

[LittleRain]

Oh I still have one problem actually, my supercic chip is not working. Flash, eprom and fuses are programmed.
I even tried it in the SMW cart with no luck.

This is how I connected it on original cart.

And here is the contents of the 629, flash, EPROM, and fuses.

I'm going to give your port to the 10f322 a go with the next revision, but I'm still kinda hoping to get this figured out. Its just not making sense to me.