(SNES)Help With Circuit for LoRom M27C322

[lidnariq]

I don't see anything obviously wrong there, sorry.

[LittleRain]

All good, I really appreciate the help you've given me.

I just tried analyzing it, tried 2 chips, a 675 and a 629.
The 629 atleast tries to respond but the 675 doesnt do squat.

I didn't bother doing the clock, although maybe I should have.

Here is the 675

And 675 with IO1 and 2 swapped.

Here is the 629

And the 629 Io swapped, which weirdly also tries to respond, but sends one less bit.

Here is the original CIC off my SMW cart, I don't understand why its working and the supercic isn't.

[LittleRain]

Just went back and did it with the clock to see if I could use a procotol anyalzer on the original CIC, man its wierd.. The clock pulses many many times before anything is sent on the IO line, which each IO pulse being many clock pulses.

Had to make another post, wouldn't let me attach these photos.

And this one is zoomed in to the first couple pulses on the IO lines.

[lidnariq]

I just tried analyzing it, tried 2 chips, a 675 and a 629.
The 629 atleast tries to respond but the 675 doesnt do squat.

The '675 has an ADC and some hardware that disables the digital inputs by default. If you want to use a '675 instead of a '629, you'll have to include an instruction to fix that.

(The supercic firmware for '629 already has this code to keep its analog comparator from precluding the digital inputs:

Code: Select all

        movlw   0x07    ; GPIO2..0 are digital I/O (not connected to comparator)
        movwf   CMCON

but you'd need to add clrf ANSEL after the banksel TRISIO in order to make this work on a '675)

The clock pulses many many times before anything is sent on the IO line, which each IO pulse being many clock pulses.

The NES and SNES CIC don't separate the two lines into "clock" and "data"; they're instead just "the other side must drive this line high/low after this many master clocks".

Only the N64 CIC behaves like half-duplex SPI.

[LittleRain]

The '675 has an ADC and some hardware that disables the digital inputs by default. If you want to use a '675 instead of a '629, you'll have to include an instruction to fix that.

(The supercic firmware for '629 already has this code to keep its analog comparator from precluding the digital inputs:

Code: Select all

        movlw   0x07    ; GPIO2..0 are digital I/O (not connected to comparator)
        movwf   CMCON

but you'd need to add clrf ANSEL after the banksel TRISIO in order to make this work on a '675)

Ah thats great to know.
When I ordered the chips, I ordered a SOP and DIP, but for some reason the seller sent me 675 for the DIPs instead of the 629 I ordered.
I asked the seller, and they said it could use the same binary, which is only half correct.

The NES and SNES CIC don't separate the two lines into "clock" and "data"; they're instead just "the other side must drive this line high/low after this many master clocks".

Only the N64 CIC behaves like half-duplex SPI.

Ah very interesting. As soon as I saw it I realized it wasn't SPI, so it was confusing me quite a bit for what it could be.


Well, I guess I'm going to try and order new IC's, they are probably counterfeit or something and maybe the internal oscillator is off by a bit.

[lidnariq]

Well, I guess I'm going to try and order new IC's, they are probably counterfeit or something and maybe the internal oscillator is off by a bit.

It doesn't use the internal oscillator; it uses the 3-or-4MHz clock provided by the SNES to run...

Where did you get the hex file you're trying to use? I only see the source code in ikari01's repository.

If you're not comfortable setting up the assembler (although the '629 and '675 are old enough you should be able to use gputils gpasm), I could add the instruction I mentioned and attach a version for the '675 here.

I also see that ikari01 changed the timing in the past couple years to something that he says is marginally more tolerant, but that shouldn't be causing the problems you're seeing.

[LittleRain]

]It doesn't use the internal oscillator; it uses the 3-or-4MHz clock provided by the SNES to run...

Oh very interesting. So is pin 56 and 57 both outputting clock from the SNES?
I downloaded an eagle library for the cartridge board shape/pins, and I noticed somethings are labeled differently than in the asm file.
For example Reset is CICIN, and both CICIO are CICOUT1/2, so I'm now wondering if CICCLK is really just another CPUCLK.

https://sd2snes.de/blog/cool-stuff/supercic

]
Where did you get the hex file you're trying to use? I only see the source code in ikari01's repository.

I got it from the SD2SNES website.
https://sd2snes.de/blog/cool-stuff/supercic
If you look in the comments they are all talking about 629.

I did see a bunch of stuff about a supercic that used a 14 or 16 pin PIC MCU, and for a while I thought I might have the binary for that, but I'm having doubts because I think people would have mentioned that on that page..

Edit: Oh wow, he included the verilog files as well for the SD2SNES.
I've just started dabling in CPLD's, pretty cool he released that.

If you're not comfortable setting up the assembler (although the '629 and '675 are old enough you should be able to use gputils gpasm), I could add the instruction I mentioned and attach a version for the '675 here.

Thanks for the offer, I probably could get it set up pretty easily, but luckily my board uses the SOP package, which they did send me a 629 in SOP, but not the DIP.
And I just ordered more 629, as well as the 322.

I also see that ikari01 changed the timing in the past couple years to something that he says is marginally more tolerant, but that shouldn't be causing the problems you're seeing.

Ah that's good to know, maybe the latest is on github. I'll give that a go.

[lidnariq]

Oh very interesting. So is pin 56 and 57 both outputting clock from the SNES?

On the SNES, I'd call pins as follows:
cart 24: CIC I/O #2
cart 25: CIC +RESET (supercic uses falling edge)
cart 55: CIC I/O #1
cart 56: CIC CPU clock (either 24576000÷8, in later SNESes, from the APU; or 4MHz, from a 4MHz ceramic resonator)
In contrast:
cart 57: S-CPU 65816 φ2: only high if either /RD or /WR are low. It has neither constant timing nor a 50% duty cycle.

I did see a bunch of stuff about a supercic that used a 14 or 16 pin PIC MCU, and for a while I thought I might have the binary for that, but I'm having doubts because I think people would have mentioned that on that page..

The 14-pin PIC is a replacement for the CIC in the SNES, allowing the console to automatically switch between 50 and 60Hz modes depending on the cartridge CIC.

[LittleRain]

On the SNES, I'd call pins as follows:
cart 24: CIC I/O #2
cart 25: CIC +RESET (supercic uses falling edge)
cart 55: CIC I/O #1
cart 56: CIC CPU clock (either 24576000÷8, in later SNESes, from the APU; or 4MHz, from a 4MHz ceramic resonator)
In contrast:
cart 57: S-CPU 65816 φ2: only high if either /RD or /WR are low. It has neither constant timing nor a 50% duty cycle.

Ah, so even though its a different speed, because the CIC is based on clock cycles it doesn't matter, correct?

The 14-pin PIC is a replacement for the CIC in the SNES, allowing the console to automatically switch between 50 and 60Hz modes depending on the cartridge CIC.

Makes sense, I gotta stop skipping over stuff so fast...


So the cic key hex is not included on that github page, looks like I will have to get the compiler running.
Edit: I just noticed there is snescic-key.asm, as well as supercic-key.asm, do you know why that is?

Edit2: Ok so I'm trying to compile with gpasm, I'm trying with this command. I think it should be all I need, but all that pops up is the command list, no errors or anything like that.

gpasm -p p12f629 -a inhx8m -o supercic-key.hex -P supercic.asm

Edit3: Got it...

gpasm -p p12F629 supercic-key.asm

I still think my command should have worked.

[lidnariq]

Ah, so even though its a different speed, because the CIC is based on clock cycles it doesn't matter, correct?

Right. Everything's in terms of number of cycles, not numbers of seconds.

Edit: I just noticed there is snescic-key.asm, as well as supercic-key.asm, do you know why that is?

Only by comparing the two.
Looks like "supercic" includes "pair mode":

SuperCIC pair mode: when a SuperCIC lock and SuperCIC key detect each other they both switch both of the data pins to inputs. The lock then passes through data i/o 0 to SNES 50/60Hz and data i/o 1 to an optional D4 output (for overriding the 213f register using additional hardware). This makes it possible to switch 50/60Hz and D4 from the cartridge slot, e.g. by connecting an additional MCU to the CIC data lines. Of course, they have to be tristated for normal (non-passthrough) operation.

I admit I'm not certain when this behavior would be useful.

Also, "snescic-key" is older and doesn't look to have been re-fixed after the change in october 2015 breaking both key implementations.

[LittleRain]

Edit: I just noticed there is snescic-key.asm, as well as supercic-key.asm, do you know why that is?

Only by comparing the two.
Looks like "supercic" includes "pair mode":

SuperCIC pair mode: when a SuperCIC lock and SuperCIC key detect each other they both switch both of the data pins to inputs. The lock then passes through data i/o 0 to SNES 50/60Hz and data i/o 1 to an optional D4 output (for overriding the 213f register using additional hardware). This makes it possible to switch 50/60Hz and D4 from the cartridge slot, e.g. by connecting an additional MCU to the CIC data lines. Of course, they have to be tristated for normal (non-passthrough) operation.

I admit I'm not certain when this behavior would be useful.

Also, "snescic-key" is older and doesn't look to have been re-fixed after the change in october 2015 breaking both key implementations.

Hmm, well I wonder why mine isn't working if this is the "fixed" version.
I've compiled the latest github source, and it verifies with my chip contents that was programmed with last hex. Something funny is going on.

Maybe it is the chip I'm using. Could have slight timing differences if its counterfeit, am I wrong?

[LittleRain]

Hey I got it working!!

I compiled version 1.10 and its working great.

Thank you so much, I would have never fixed it if you didnt mention gpasm and the github page.

[LittleRain]

Hey lidnariq, how do you program the 322?
Do you use a parallel programmer, or something like a pickit or snap?
I have a snap, but I guess either way I'll have to make an adapter.

[lidnariq]

Parallel UVEPROMs like the 27C322 require a parallel programmer. What with having 42 pins, it won't quite fit in the inexpensive programmers (MiniPro) you can buy right now (which have only 40 pins)

I've been using an old TOP3000 programmer. You can probably find some other options.

[LittleRain]

Oops, I meant the Pic10F322.

I'm working on my second revision now, was thinking about using your 10f322 CIC code.
I see it has ICSPCLK/DAT, so I'm pretty sure its compatible with my snap, and i see VPP so I'm assuming can be HV programmed as well, just wondering how you yourself does it.