iNes mapper 159 with 512KiB PRG

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mightydidz
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Joined: Wed Jan 24, 2018 12:04 pm

iNes mapper 159 with 512KiB PRG

Post by mightydidz » Sun Dec 20, 2020 5:34 pm

I want to know if it would be possible on real hardware to have a 512KiB of PRG ROM.
I'll use a DragonBallZ PCB with contain a LZ93D50 and 24C02 EEPROM.

LZ93D50 Pinout
https://wiki.nesdev.com/w/index.php/Ban ... 50_pinout

Mapper 153 can bankswitch up to 512KiB but is using CHR-RAM instead of CHR-ROM.
Both Jump-2 and SD Gundam Gaiden are using Bandai LZ93D50 chip and pinout is really similar.

I'd like to make this translation on real hardware
https://www.romhacking.net/translations/5482/

I'm wondering if it would be possible to rewire some pins on LZ93D50 to still have a 128/256 KiB of CHR-ROM and increase PRG to 512KiB?

Thanks for the help

lidnariq
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Re: iNes mapper 159 with 512KiB PRG

Post by lidnariq » Sun Dec 20, 2020 5:40 pm

https://wiki.nesdev.com/w/index.php/Use ... ts#LZ93D50

You will need three extra parts to modify an existing board to be compatible with the translation's stupid oversize definition.

NewRisingSun
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Re: iNes mapper 159 with 512KiB PRG

Post by NewRisingSun » Sun Dec 20, 2020 6:15 pm

Alternatively, because this first Knight Gundam game only uses 128 KiB of CHR-ROM, you could connect the LZ93D50's CHR A17 pin to PRG-ROM A18. But then you would have to modify the game code accordingly. But that would switch the entire $8000-$FFFF CPU address range, without the fixed bank at $C000-$FFFF.

mightydidz
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Re: iNes mapper 159 with 512KiB PRG

Post by mightydidz » Sun Dec 20, 2020 6:54 pm

I guess using a 74'138, a 74'259 and a 74'32 seems easier.

Can someone help me figure the schematic to decode
writes when (A & 0x800F) == 0x8008?

I saw something similar for a taito repro but it's not using the same parts
Attachments
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lidnariq
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Re: iNes mapper 159 with 512KiB PRG

Post by lidnariq » Sun Dec 20, 2020 7:08 pm

mightydidz wrote:
Sun Dec 20, 2020 6:54 pm
Can someone help me figure the schematic to decode
writes when (A & 0x800F) == 0x8008?
What's keeping you from figuring out this yourself?

mightydidz
Posts: 74
Joined: Wed Jan 24, 2018 12:04 pm

Re: iNes mapper 159 with 512KiB PRG

Post by mightydidz » Sun Dec 20, 2020 7:18 pm

I'm not an electronic engineer nor a romhacker. I barely understand hex and addressing. I'm still learning and like those challenges.

I would be happy to learn tough. :D

lidnariq
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Location: Seattle

Re: iNes mapper 159 with 512KiB PRG

Post by lidnariq » Sun Dec 20, 2020 7:33 pm

First step is convert these two numbers from hex to binary.

0x800F = 0b1000_0000_0000_1111

The ones in this binary number are the address lines you need to care about.

0x8008 = 0b1000_0000_0000_1000

The ones in this binary number indicate whether each address line needs to be high or low.

"Decode Writes" = R/W must be low

Famicom doesn't give direct access to A15, so you have to use /ROMSEL instead. Fortunately, if /ROMSEL is low, you know that A15 and M2 are both high.

Does this explain anything?

mightydidz
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Re: iNes mapper 159 with 512KiB PRG

Post by mightydidz » Sun Dec 20, 2020 8:36 pm

That a start, thank you for the explanation, but I still doesn't know how to convert this into a schematic.

I guess I'll have to use CPU A0~A3 and A15(! /romsel) for the decoder. For the rest, I have no clue.

mightydidz
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Re: iNes mapper 159 with 512KiB PRG

Post by mightydidz » Mon Dec 21, 2020 6:41 am

At least, are 74'138, 74'259 and 74'32 the chips I need?
I'll check datasheet and truth table to see how they work.

Thanks

lidnariq
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Re: iNes mapper 159 with 512KiB PRG

Post by lidnariq » Mon Dec 21, 2020 12:13 pm

mightydidz wrote:
Mon Dec 21, 2020 6:41 am
74'259
No. The 74'259 is an "addressable" latch.

mightydidz
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Re: iNes mapper 159 with 512KiB PRG

Post by mightydidz » Mon Dec 21, 2020 12:43 pm

I've read your post couple of times
https://wiki.nesdev.com/w/index.php/Use ... ts#LZ93D50

If I understand correctly its the same hardware as mmc4?
MMC4
74'138, 4+ bit latch, 74'32. 74'138 decodes writes to $Axxx. Latch latches D4 through D7 during those writes. 74'32 implements fixed upper bank.

Sunsoft 3 and Sunsoft 4
Same hardware. 74'138 decodes writes to $F8xx or $Fxxx, respectively. Otherwise identical.

Both ASICs already latch D4 and present the latched value on the bottom-right pin (SS3: 22, SS4: 21). An external 74'1g32 will expand PRG capacity to 512KB.

VRC3
Same hardware, decode writes to $Fxxx. ASIC only implements three bits, so to maximize the address space, a full five bits of latch and OR gates are needed.

LZ93D50
Same hardware. Decode writes when (A & 0x800F) == 0x8008
you gave me additional explanations here.
0x800F = 0b1000_0000_0000_1111

The ones in this binary number are the address lines you need to care about.

0x8008 = 0b1000_0000_0000_1000

The ones in this binary number indicate whether each address line needs to be high or low.

"Decode Writes" = R/W must be low

Famicom doesn't give direct access to A15, so you have to use /ROMSEL instead. Fortunately, if /ROMSEL is low, you know that A15 and M2 are both high.
0x800F = 0b1000_0000_0000_1111: means that I need to carry about A0 through A3 and A15?
0x8008 = 0b1000_0000_0000_1000: I'm not 100% sure about this one...
The ones in this binary number indicate whether each address line needs to be high or low.
A0 through A2 needs to be low, A3 and A15 high? Am I correct?
Famicom doesn't give direct access to A15, so you have to use /ROMSEL instead. Fortunately, if /ROMSEL is low, you know that A15 and M2 are both high.
When /ROMSEL is low, both A15 and M2 are high? I need to realize this condition with the decoder also?

Can you confirm I'm on the right track? If so, What's next, the latch?
I cannot use an "addressable" latch. What kind of latch I need to use? a D type latch?

lidnariq
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Re: iNes mapper 159 with 512KiB PRG

Post by lidnariq » Mon Dec 21, 2020 1:55 pm

mightydidz wrote:
Mon Dec 21, 2020 12:43 pm
A0 through A2 needs to be low, A3 and A15 high? Am I correct?
Correct!
When /ROMSEL is low, both A15 and M2 are high? I need to realize this condition with the decoder also?
NES indicates a valid data bus by a falling edge of M2. Which means that a rising edge of /ROMSEL also indicates a valid data bus.
I cannot use an "addressable" latch. What kind of latch I need to use? a D type latch?
Any D latch, D register, transparent latch, so on. 74x74, 74x373, 74x374, 74x573, 74x1g79, there are probably more of these than any other single 74xxx part.

mightydidz
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Re: iNes mapper 159 with 512KiB PRG

Post by mightydidz » Mon Dec 21, 2020 2:34 pm

How many lines I need the decoder to have?
A0 through A2 needs to be low
A3 and A15 needs to be high.
Do I need 5 lines or with 3 selects and 3 enable I could make it?

I've check 74'138 datasheet
https://www.ti.com/lit/ds/symlink/sn74hct138.pdf

If I connect A3, /ROMSEL and R/W on enable lines
and A0, A1 and A2 on select lines
would it work for the decoder?

I guess next step is outputting decoders Y lines to the latch D inputs?

lidnariq
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Re: iNes mapper 159 with 512KiB PRG

Post by lidnariq » Mon Dec 21, 2020 2:42 pm

mightydidz wrote:
Mon Dec 21, 2020 2:34 pm
If I connect A3, /ROMSEL and R/W on enable lines
and A0, A1 and A2 on select lines
would it work for the decoder?
Yup.
I guess next step is outputting decoders Y lines to the latch D inputs?
You'll have to figure out which /Yn output to use. But it's to the ↑clock or LATCH input on the part, not their D=data input.

mightydidz
Posts: 74
Joined: Wed Jan 24, 2018 12:04 pm

Re: iNes mapper 159 with 512KiB PRG

Post by mightydidz » Mon Dec 21, 2020 2:59 pm

According to 74'138 datasheet it would be Y0 output?

I'm now reading 74'373 datasheet
https://www.ti.com/lit/ds/symlink/sn74h ... SN74HCT373
The eight latches of the ’HCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components
I'm guessing the decoder Y0 would be used for the latch-enable input?

I'm still uncertain about the other latch inputs/outputs. How do I use them for my application?
Thanks

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