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PostPosted: Sun Aug 19, 2018 4:50 pm 
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Joined: Sun Sep 07, 2008 7:27 am
Posts: 494
Location: Seatlle, WA, USA
Hello. My emulator currently passes blargg's CPU opcode test, but fails some of the "ppu_vbl_nmi.nes" tests.

Test #2 documentation (from the source):

Code:
; Verifies time VBL flag is set.
;
; Reads $2002 twice and prints VBL flags from
; them. Test is run one PPU clock later each time,
; around the time the flag is set.
;
; ^@T+ 1 2
; 00 - V
; 01 - V
; 02 - V
; 03 - V   ; after some resets this is - -
; 04 - -   ; flag setting is suppressed
; 05 V -
; 06 V -
; 07 V -
; 08 V -


My output:
Code:
$ ./output/testsuite
Unhandled PPU.write(0002, 00)
FAIL: src/emulator/test/PpuVblNmiCart_t.cc:86  0x00(0x00) != status(0x01)
  T+ 1 2
  00 - V
  01 - V
  02 - V
  03 - V
  04 - V
  05 V -
  06 V -
  07 V -
  08 V -
  4103C340
  02-vbl_set_time
  Failed
  While running test 2 of 10
Total tests: 354
Failed tests: 1


My own PPU VBL timing unit test [1] passes.

I assume that test #2 is testing that the emulator properly implements the race condition described in [2]. Can anyone confirm this hypothesis?

[1] https://pastebin.com/rD4PTeG6
[2] https://wiki.nesdev.com/w/index.php/NMI


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PostPosted: Sun Aug 19, 2018 5:36 pm 
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Formerly Fx3
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Joined: Fri Nov 12, 2004 4:59 pm
Posts: 3155
Location: Brazil
If I'm not wrong, it's the same question here.
viewtopic.php?f=3&t=17663


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PostPosted: Mon Aug 20, 2018 1:33 am 
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Joined: Mon Aug 20, 2018 1:23 am
Posts: 4
I'm trying to fix the exact same bug right now in my emu.
Some info: check out "VBL FLag Timing" at this page http://wiki.nesdev.com/w/index.php/PPU_frame_timing


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