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PostPosted: Sat Jan 01, 2005 1:48 pm 
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Joined: Wed Nov 17, 2004 12:34 pm
Posts: 41
Simple question actually. Should the effects of a processor cycle be immediate or when the cycle ends (which is a 3 pixel difference). For example

INC Instruction (Absolute addressing):

Cycle 1: Fetch Opcode
Cycle 2: Fetch Low Byte of Address
Cycle 3: Fetch High Byte of Address
Cycle 4: Read from Address
Cycle 5: Write old value back to Address
Cycle 6: Write new value back to Address

So let's pretend the address is 2007, the bastards. What I'm saying is should the write take effect on the PPU in ppu cycle 12 or ppu cycle 15?
I.E. Should 12 pixels be rendered before the write takes effect or 15?

To me it seems like it should be 15, since the ppu shouldn't know the write to that memory location occurred until the processor cycle has completely finished...however some people have spoken of otherwise...

It could be something freaky like MID-CYCLE! AHHHH

:D
Thanks :)


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PostPosted: Sat Jan 01, 2005 2:04 pm 
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Joined: Mon Sep 20, 2004 11:13 am
Posts: 134
Location: Sweden
I haven't got an answer, but...
I've been experimenting with mid-cycle writes myself but have not been able to come to any conclusion. Right now, I let PPU reads take effect on the first of the 3 PPU cycles, and writes take effect on the last one. It seems to work fine.

I don't know how this works on a NES, but changing this actually makes a difference for me in certain roms, examples are Dizzy the adventurer, scanline.nes and Battletoads. When I first started writing my emu, I would never ever have expected mid-cycle accesses to make a difference, lol. :)

--Martin


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