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 Post subject: PPU Rendering Pipeline
PostPosted: Sat Aug 22, 2015 11:45 am 
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In attempt to improve the accuracy of my PPU implementation, I have been studying the source code of Nintendulator (PPU.cpp). I noticed that VRAM reads and writes are delayed by 3 PPU cycles:

Code:
unsigned char IOVal;
unsigned char IOMode;   // Start at 6 for writes, 5 for reads - counts down and eventually hits zero

...

IOMode -= 2;


Is the delay related to the PPU rendering pipeline?


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PostPosted: Sat Aug 22, 2015 11:54 am 
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I'm sorry if I'm derailing this thread when it just started, but what is a "pipeline" in electronics? I've been itching to ask this.


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PostPosted: Sat Aug 22, 2015 12:19 pm 
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A pipeline is a series of operations done in sequence. This usually implies that they are done independently as well, so you can have multiple items proceeding along the pipeline at the same time, each one in a different stage.

This may help: http://en.wikipedia.org/wiki/Pipeline_(computing)


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PostPosted: Sun Aug 23, 2015 12:20 am 
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It takes the PPU 2 cycles to output a full 14-bit address, so that's why accesses are delayed like that. I think the third cycle in that delay is because the CPU can initiate a fetch while the PPU is on the second of its two-cycle procedure for outputting an address, which would mean the fetch would take 3 PPU cycles to complete, instead of 2. Someone may need to fact check me on that though.


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