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PostPosted: Sat Oct 17, 2015 3:06 pm 
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In my attempts to try to understand how pattern and nametables work I've opened up a few games in FCEUXD to view the ppu memory and pattern tables. One question that i had was that if the nametable memory for a certain X,Y of the background is 0xFF (256th tile from the pattern table), how does the PPU know whether to read from the left or right pattern table? I noticed also that it looked like for DK the sprites took the left pattern table and the background the right.

The answer, I think, to my original question comes in the form of this diagram, where I see there is a flag for "Half of the sprite table" which i assume sets which half is used only for sprites and which is used for backgrounds. I'm having trouble understanding the context of this diagram though. It looks like a piece of two byte memory, but then where is that memory being read from?

This is the diagram from the nesdev wiki, this is all the section says.

Code:
PPU addresses within the pattern tables can be decoded as follows:
DCBA98 76543210
---------------
0HRRRR CCCCPTTT
|||||| |||||+++- T: Fine Y offset, the row number within a tile
|||||| ||||+---- P: Bit plane (0: "lower"; 1: "upper")
|||||| ++++----- C: Tile column
||++++---------- R: Tile row
|+-------------- H: Half of sprite table (0: "left"; 1: "right")
+--------------- 0: Pattern table is at $0000-$1FFF

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PostPosted: Sat Oct 17, 2015 3:18 pm 
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The "left" vs "right"-ness is determined by the bits in the PPUCTRL register.

(Backgrounds are always read from the half according to the $10s bit in this register. Sprites can come from left, right, or controlled by the individual sprite according to the $20s and $08s bits in the register)


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PostPosted: Sat Oct 17, 2015 3:55 pm 
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lidnariq wrote:
The "left" vs "right"-ness is determined by the bits in the PPUCTRL register.

(Backgrounds are always read from the half according to the $10s bit in this register. Sprites can come from left, right, or controlled by the individual sprite according to the $20s and $08s bits in the register)


Thanks for clearing that up. Any info on that what that diagram is trying to say?

Edit: i think i just figured it out. It refers to each 16 bit address in the VRAM: from a given address, you can derive that info based on the address alone.

I recommend an edit to the wiki that includes an example.

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