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PostPosted: Fri Dec 18, 2015 8:05 am 
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Joined: Sun Sep 19, 2004 11:12 pm
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Location: NE Indiana, USA (NTSC)
Bregalad wrote:
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The "write buffer" isn't really a buffer - the value simply floats on the internal data bus until it's ready to go out the data pins, and the PPU relies on the fact that this value takes a while to decay.

Wow I'm surprised this works at all. Sounds like really choppy electronics design, I would certainly had bad grades as a student if I ever designed a chip like that.

Then you'd end up flunking along with a lot of professional computer engineers, as a dynamic latch is a fairly common design pattern. Wikipedia's article says it's distinguished "by exploiting temporary storage of information in stray and gate capacitances. [...] Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design."

Perhaps Nintendo engineers considered 44 master clocks (11 dots) fast enough when the CPU is guaranteed not to write to $2007 more often than every 48 master clocks (4 cycles) so long as RMW instructions (ASL, LSR, ROL, ROR, INC, DEC) are not used.


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