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 Post subject: NES I/O Register address latchesPosted: Sun Jan 03, 2016 12:12 pm

Joined: Sun May 10, 2015 5:01 pm
Posts: 4
I'm trying to understand how the address latch works when dealing with PPUSCROLL and PPUADDR.

The wiki states (for SCROLL and ADDR):
Quote:
Reading the status register will clear D7 mentioned above and also the address latch used by PPUSCROLL and PPUADDR.

My question is this: Since PPUSCROLL and PPUADDR share the same latch, what happens if you mix writes to both addresses?

Example:

Write 0xa to PPUSCROLL, write 0xb to PPUADDR, then write 0xc to PPUSCROLL. What is the value of PPUSCROLL? What is the value of the latch and PPUADDR?

Is it safe to say that the PPUSCROLL and PPUADDR only get set to the value of the latch on their second write, and since the latch is shared, it's whatever the state of the latch is at that point in time? Also what happens when additional writes occur and PPUSTATUS hasn't been read (so the latch hasn't been reset)?

Example:

Write 0xa to PPUSCROLL, write 0xb to PPUSCROLL, write 0xc to PPUSCROLL, what 0xd to PPUSCROLL. What is the value of PPUSCROLL and the latch?

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 Post subject: Re: NES I/O Register address latchesPosted: Sun Jan 03, 2016 12:46 pm

Joined: Sun Apr 13, 2008 11:12 am
Posts: 7828
Location: Seattle
The exact function of each of the four possible writes to \$2005 and \$2006 are enumerated here: nesdevwiki:PPU scrolling.

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 Post subject: Re: NES I/O Register address latchesPosted: Mon Jan 04, 2016 11:14 pm

Joined: Sun May 10, 2015 5:01 pm
Posts: 4
Is PPUADDR a 16-bit register? The wiki states that you need to write to the memory mapped address (\$2006) twice to full the register with the most and least significant bytes.

The wiki almost makes it seem like PPUADDR is a 8-bit register which wouldn't be large enough to hold the full address that gets written. Is this a typo in the wiki?

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 Post subject: Re: NES I/O Register address latchesPosted: Mon Jan 04, 2016 11:42 pm

Joined: Sun Jan 22, 2012 12:03 pm
Posts: 7017
There are four related registers: PPU_scrolling#PPU_registers

The PPU address is 15-bit, and there is a second 15-bit register that holds a temporary copy of the PPU address before applying the change.

PPUADDR is not a register, it is just a name given to the port at memory address \$2006. Writing to \$2006 affects the PPU address registers in various ways. (Read the page that was just linked. lidnariq linked it too.)

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 Post subject: Re: NES I/O Register address latchesPosted: Tue Jan 05, 2016 6:45 am

Joined: Sat Feb 12, 2005 9:43 pm
Posts: 11012
Location: Rio de Janeiro - Brazil
The 6502 is an 8-bit CPU that can only read and write data one byte at a time. The \$2005/6 latch exists precisely so that the 8 bits that are writen have a different meaning on two consecutive writes.

The wiki page shows exactly which bits of the internal registers are affected on each of the 4 possible writes (\$2005 even, \$2005 odd, \$2006 even, \$2006 odd).

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