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PostPosted: Tue Jan 05, 2016 7:55 pm 
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My understanding of an NMI is that it cannot be masked/suppressed. As defined by wikipedia:

Quote:
A non-maskable interrupt (NMI) is a hardware interrupt that cannot be ignored by standard interrupt masking techniques in the system


I was reading the following documentation from http://nesdev.com/NESDoc.pdf

Quote:
NMIs are not affected by the interrupt disable bit in the status register, so execution is always interrupted when they occur [31]. However, triggering of a NMI can be prevented if bit 7 of PPU Control Register 1 ($2000) is clear.


Isn't this contradictory? If it can be suppressed, isn't it technically not an NMI? I must be misreading this...


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PostPosted: Tue Jan 05, 2016 8:01 pm 
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NMI is an input signal on the CPU, and yeah, as the name implies, it can't be masked or disabled by the CPU. On the PPU, NMI is an output signal. Disabling it by writing to that PPU register means the PPU simply doesn't send the signal to the CPU.


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PostPosted: Tue Jan 05, 2016 8:02 pm 
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And usually a game's reset code will tell the PPU not to generate NMI within the first half dozen instructions:
Code:
reset:
  sei
  cld
  lda #$00
  sta $2000  ; disable NMI
  sta $2001  ; disable rendering


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PostPosted: Tue Jan 05, 2016 8:10 pm 
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Memblers wrote:
NMI is an input signal on the CPU, and yeah, as the name implies, it can't be masked or disabled by the CPU. On the PPU, NMI is an output signal. Disabling it by writing to that PPU register means the PPU simply doesn't send the signal to the CPU.


So to clarify -- If bit 7 of $2000 is clear, then ISR I have defined in FFFA/FFFB won't get run, and the 7 cycles it takes to perform an NMI won't occur... So no extra cycles will be expended.


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PostPosted: Tue Jan 05, 2016 8:13 pm 
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Right, in that case the CPU will see no NMI signal, so there's nothing to do from CPU's point of view.


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