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PostPosted: Tue Mar 08, 2016 12:42 pm 
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According to the 6502 documentation some instructions takes +1 clockcycle "if page boundary is crossed."
I am not entirely sure how this work.

For example:
Opcode 0x7D is affected (ADC absolute,X)

Is the extra cycle "triggered" with this example or have I got it wrong?
Code:
ldx #1
adc $00FF,x

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PostPosted: Tue Mar 08, 2016 12:46 pm 
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In http://nesdev.com/6502_cpu.txt , scroll down to "Absolute indexed addressing" :
Quote:
Code:
 Absolute indexed addressing

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,
                        LAX, LAE, SHS, NOP)

        #   address  R/W description
       --- --------- --- ------------------------------------------
        1     PC      R  fetch opcode, increment PC
        2     PC      R  fetch low byte of address, increment PC
        3     PC      R  fetch high byte of address,
                         add index register to low address byte,
                         increment PC
        4  address+I* R  read from effective address,
                         fix the high byte of effective address
        5+ address+I  R  re-read from effective address

       Notes: I denotes either index register (X or Y).

              * The high byte of the effective address may be invalid
                at this time, i.e. it may be smaller by $100.

              + This cycle will be executed only if the effective address
                was invalid during cycle #4, i.e. page boundary was crossed.


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PostPosted: Tue Mar 08, 2016 1:37 pm 
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Joined: Wed Mar 31, 2010 12:40 pm
Posts: 207
oRBIT2002 wrote:
Is the extra cycle "triggered" with this example or have I got it wrong?
Code:
ldx #1
adc $00FF,x


That would do it. Basically this means that the addition of the low address byte and the offset carried, which causes the high byte to need to be corrected (hence the extra cycle).

The following pseudo-code simulates an absolute address + x pattern (for opcodes with varying timing):

Code:
// ea.w = effective address (16-bit) formed by ((ea.h * 256) + ea.l)
// ea.l = effective address low (8-bit)
// ea.h = effective address high (8-bit)

ea.l = read(pc++); // cycle 1
ea.h = read(pc++); // cycle 2

ea.l = (ea.l + x) & 0xff;

if (ea.l < x) { // this is only true when the above addition "wraps around", or carries
  read(ea.w); // cycle 3 (optional)
  ea.h = (ea.h + 1) & 0xff;
}


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PostPosted: Tue Mar 08, 2016 1:53 pm 
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Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19116
Location: NE Indiana, USA (NTSC)
There is a complication, however. Most 6502 assemblers (other than MagicKit-family ones such as NESASM) will "correct" the instruction adc $00FF,x to the instruction adc $FF,x, which uses zero page indexed addressing mode. Zero page indexed addressing mode is four cycles period because it wraps within $0000-$00FF. To force absolute addressing mode, you need to use assembler-specific syntax. For example, in ca65, the a: prefix forces an address to be absolute. For example, the instruction would be written adc a:$FF,x.


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