It is currently Mon Oct 23, 2017 3:47 pm

All times are UTC - 7 hours





Post new topic Reply to topic  [ 11 posts ] 
Author Message
PostPosted: Sat Apr 09, 2016 9:47 am 
Offline
Formerly Fx3
User avatar

Joined: Fri Nov 12, 2004 4:59 pm
Posts: 3064
Location: Brazil
opcode $13 (SLO, zero page Y indexed), should take 8 cycles, but I'm getting only 6!
Why???

- Reading the opcode takes 1 cycle;
- decoding the adressing mode takes 2 cycles;
- a SLO takes 4 cycles:
Code:
CPUOP(SLO1)
  value = _readvalue(offset); //4th
  _writevalue(offset, value); //5th
  ASL(value);
  writevalue(offset, value); //6th
  //ORA0
  cpu->A |= value;
  SET_SZ_FLAGS(cpu->A);
OPEND


Top
 Profile  
 
PostPosted: Sat Apr 09, 2016 10:58 am 
Offline

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19122
Location: NE Indiana, USA (NTSC)
$13 is slo (dd),y (zero page indirect indexed), not slo dd,y (zero page indexed). The dd,y addressing mode exists only for the ldx, stx, lax, and sax instructions.

Thus slo ($02),y takes eight cycles:
  1. Read slo (dd),y opcode
  2. Read address of pointer
  3. Read low byte of pointer from dd
  4. Read high byte of pointer from (dd+1 .mod $100)
  5. Read old value from partly-formed address
  6. Read old value from correct address
  7. Write old value while calculating new value
  8. Write new value


Top
 Profile  
 
PostPosted: Sat Apr 09, 2016 2:37 pm 
Offline
Formerly Fx3
User avatar

Joined: Fri Nov 12, 2004 4:59 pm
Posts: 3064
Location: Brazil
My reference isn't correct after all...
http://www.oxyron.de/html/opcodes02.html

Using this one (old, but gold) now.
http://nesdev.com/6502_cpu.txt


Top
 Profile  
 
PostPosted: Wed Apr 13, 2016 3:31 pm 
Offline
User avatar

Joined: Sat Jul 12, 2014 3:04 pm
Posts: 936
*looks at table*
Quote:
$13: SLO, izy 8

Error being...?


Top
 Profile  
 
PostPosted: Wed Apr 13, 2016 3:58 pm 
Offline

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19122
Location: NE Indiana, USA (NTSC)
A note at the top of the the oxyron table states that "izy" means (dd),Y. It appears to stand for indirect zero page Y.


Top
 Profile  
 
PostPosted: Wed Apr 13, 2016 5:01 pm 
Offline
Formerly Fx3
User avatar

Joined: Fri Nov 12, 2004 4:59 pm
Posts: 3064
Location: Brazil
SLO always execute the 4th cycle. Normally, this cycle is only executed on page crossing.


Top
 Profile  
 
PostPosted: Wed Apr 13, 2016 5:05 pm 
Offline

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19122
Location: NE Indiana, USA (NTSC)
What do STA aaaa,X and INC aaaa,X have in common? They always perform the dummy read while adding the index to the address. Likewise, SLO (dd),Y and other unofficial RMW+ALU instructions with (dd),Y are like STA (dd),Y in that they always perform the dummy read.


Top
 Profile  
 
PostPosted: Wed Apr 13, 2016 6:09 pm 
Offline
Formerly Fx3
User avatar

Joined: Fri Nov 12, 2004 4:59 pm
Posts: 3064
Location: Brazil
Dummy reads with the high byte of the address not fixed yet.


Top
 Profile  
 
PostPosted: Thu Apr 14, 2016 5:36 am 
Offline
Formerly ~J-@D!~
User avatar

Joined: Sun Mar 12, 2006 12:36 am
Posts: 445
Location: Rive nord de Montréal
The dummy read is always done, even if the address needs no fixing. For example, sta addr, x for x = 0 reads then writes to addr, always.


Top
 Profile  
 
PostPosted: Thu Apr 14, 2016 5:43 am 
Offline

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19122
Location: NE Indiana, USA (NTSC)
For pure read instructions using indexed addressing modes (ORA, AND, EOR, ADC, LDA, CMP, SBC, LDX, LDY), the dummy read is skipped if not needed. (Actually, it's the correction read that's skipped once the 6502 realizes that the dummy read was correct.) But for write instructions (STA, STX, STY), read-modify-write instructions (ASL, ROL, LSR, ROR, DEC, INC), and unofficial read-modify-write plus ALU instructions (SLO, RLA, SRE, RRA, DCP, ISC), the dummy read is always performed.


Top
 Profile  
 
PostPosted: Thu Apr 14, 2016 6:08 am 
Offline
Formerly ~J-@D!~
User avatar

Joined: Sun Mar 12, 2006 12:36 am
Posts: 445
Location: Rive nord de Montréal
Hmm, a part of my post was left in my head, and not posted :P. I wanted to say that all indexed instructions that involve a write always do the dummy read, because it would be wrong to write at a wrong address. Exception is indexed indirect (OP (zp, x)), because the indexing is done to the indirect address, not to the effective address.


Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 11 posts ] 

All times are UTC - 7 hours


Who is online

Users browsing this forum: No registered users and 5 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group