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 Post subject: Re: DMA 'on write cycle'
PostPosted: Wed Apr 20, 2016 4:46 pm 
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Joined: Wed Nov 10, 2004 6:47 pm
Posts: 1845
Zepper wrote:
I mean... in easy words... you write a test rom... and someone would run it in a NES.


I'm not really testing stuff as much as I'm trying to observe behavior.

Quote:
I don't know a thing about the accuracy level when using a PowerPak-like device, instead of a SMB-for-tests cartridge set.


PowerPak is no good for testing anything mapper related -- or anything cartridge side (since it is also just an emulator) -- nor is it good for testing power-on state (since the PowerPak has to run its own code before it passes control to your ROM)

But for testing any other core NES functionality, it should be fine.


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 Post subject: Re: DMA 'on write cycle'
PostPosted: Fri Apr 22, 2016 4:44 am 
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Posts: 17
Hi Disch

If the DMA-unit works like you assumed this behavior can cause errors.
Lets say the CPU executes the Opcode "LDA $2002" and the DMA gets active
in that moment the CPU requests the PPU for $2002. With the "next cpu tick"
the PPU returns PPUSTATUS with a set Vblank-Bit and clears Vblank internally.
In this next tick the CPU gets holded, the DMA takes control over the addr/data
bus and requests a byte of audio stream which will be available with the next cpu
tick. With this third tick the request to $2002 have to be repeated, cause the
previously requested byte got lost. But now the PPU returns a PPUSTATUS
without VBlank set which can result in faulty behavior of the software.

Chris


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 Post subject: Re: DMA 'on write cycle'
PostPosted: Fri Apr 22, 2016 5:33 am 
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Posts: 1058
Location: Minneapolis, MN
Did you read this??
viewtopic.php?f=3&t=9030&hilit=+Visual2A03


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 Post subject: Re: DMA 'on write cycle'
PostPosted: Fri Apr 22, 2016 5:48 am 
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Joined: Fri Mar 18, 2016 3:59 am
Posts: 17
Sorry, missed that thread. But very interesting.
Forget everything i wrote before. It includes my considerations completely.


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