Zepper wrote:Disch wrote: What do you mean by "3 PPU cycles left to run"?
Really!? Okay, so... "for each CPU cycle, the NTSC PPU runs for 3 cycles".
Language barrier? =x
"left to run" to me means there are 3 more cycles that need to execute until something interesting happens.
"Y happens with 3 cycles left to run"
==
"Y happens 3 cycles before X"
and I didn't know what 'X' was.
There's a special (?) case about CPU/PPU alignment, where there was a write to $2000 (enabling NMI) and the PPU is at VBlank start cycle (0).
This shouldn't matter.
Given the below code:
Code: Select all
; NMIs disabled here
LDA #$80
STA $2000 ;enable NMI
NOP
As you know, the actual write to $2000 occurs on the very last cycle of the STA instruction.
This means it is
already too late for the NMI to happen because the CPU has already started the process of fetching the next byte.
So if the $2000 write
AND the NMI happen at the same time... your emu can chose which one to do first... but regardless of which one you choose, the NMI will not happen until
after the NOP
Example:
Option 1 (write before NMI):
- $2000.7 written with bit 7 high enables NMIs
- $2002.7 goes high at start of VBlank
- $2002.7 transitions from 0->1 while $2000.7 is high --
this triggers an NMI
- NOP completes because of CPU pipelining
- NMI executes
Option 2 (NMI before write):
- $2002.7 goes high as VBlank starts.
- NMIs are disabled, so no NMI
- $2000 is written with bit 7 high
- $2000.7 makes low->high transition while $2002.7 is high --
this triggers an NMI
- NOP completes because of CPU pipelining
- NMI executes
As you can see, no matter which you do first, the result is the same. The following instruction executes, then NMI triggers. It doesn't matter if it happens on the same cycle as a $2000 write.