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 Post subject: fpgaNES - project status
PostPosted: Mon May 02, 2016 4:59 am 
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Joined: Fri Mar 18, 2016 3:59 am
Posts: 17
Hi,

The first stage of my fpgaNES is nearly complete and you will find my work under:

https://github.com/Feuerwerk/fpgaNES


It is based on the development board Cyclone V GX Starter Kit by Terasic with an
Altera Cyclone V on board. It features plenty of memory, an HDMI out and an analog
Audio Codec. For some reason they decided to not connect the audio pins of the
ADV7513 HDMI chip to the FPGA. But kindly they added solder points for the audio pins
so i was able to access them trough some GPIO pins of the FPGA getting 44.1 kHz audio
samples directly through the HDMI connection. The hdmi video resolution is 640x480 at a
framerate of 60 Hz having 2x2 display pixels per nes pixel. Beside the HDMI audio pins i
soldered a NES Four Score to the GPIO-Port to simply plug/unplug the controllers to the
FPGA. I decided to use VHDL as programming language.

In the next stage i will add support for changing the games modules. Either i will
make use a GPIO daughter board and connect it to an original NES module header
but i’m unsure if i need a bunch of level shifters since the game modules work with 5V and
my FPGA board / GPIO daughter board with 3.3V or i will use the onboard micro sdcard reader
and add support for several mappers and directly load nes files from the sdcard.

What works:

- https://github.com/Klaus2m5/6502_65C02_functional_tests
- Super Mario Brothers 1
- blargg_ppu_tests_2005.09.15b
- NEStress
- ppu_vbl_nmi
- sprite_hit_tests_2005.10.05
(Audio test roms are the next things on my todo list)


What is currently not implemented:

- PPU color emphasize
- low / high pass filter (i added both with the equations blargg published but for some reason they don’t work)
- Support for PAL games (currently i only implemented the clock speed and lookup tables for NTSC games)


Feel free to point me to problems or bad code, since i made this project to learn VHDL and FPGAs.


Have fun
Chris


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Last edited by Feuerwerk42 on Mon May 02, 2016 8:35 am, edited 4 times in total.
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PostPosted: Mon May 02, 2016 5:02 am 
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Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19341
Location: NE Indiana, USA (NTSC)
Feuerwerk42 wrote:
The video resolution is 640x480 @ 50 Hz
[...]
What is currently not implemented:

[...]
- PAL (currently only NTSC works)

Somehow I'm not understanding.

Quote:
with a 2x2 display pixel per nes pixel

How hard would it be to put in interpolation to get a 2.29x2 display pixel, so that the magnifying glass in Dr. Mario is closer to circular?


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PostPosted: Mon May 02, 2016 5:15 am 
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Joined: Fri Mar 18, 2016 3:59 am
Posts: 17
@tepples

Quote:
Somehow I'm not understanding.


I modified my original post. I hope it becomes clearer.


Quote:
How hard would it be to put in interpolation to get a 2.29x2 display pixel, so that the magnifying glass in Dr. Mario is closer to circular?


Currently i haven't thought about picture enhancements but two days ago i found Ludde's FPGA project (http://fpganes.blogspot.de) and he already
added an algorithm called HQ2X with pretty amazing results. I think i will add this too. What would be a good algorithm to enhance stretched images?


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PostPosted: Mon May 02, 2016 8:17 am 
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Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19341
Location: NE Indiana, USA (NTSC)
Feuerwerk42 wrote:
Currently i haven't thought about picture enhancements but two days ago i found Ludde's FPGA project (http://fpganes.blogspot.de) and he already
added an algorithm called HQ2X with pretty amazing results. I think i will add this too. What would be a good algorithm to enhance stretched images?

With non-blurring pixel art interpolation algorithms, such as Scale2x or hq2x, perhaps the best policy is to run the enhancement and then do a linear horizontal stretch on the output.

As for 50 vs. 60, if your panel only takes 50 Hz input but you want compatibility with NTSC ROMs, consider implementing Dendy mode. This uses the same PPU dot to CPU cycle ratio (3:1), the same APU noise and DMC periods, the same NMI-to-frame-start period, and almost the same overall clock rate as the NTSC NES. But it makes the post-render period 51 lines long instead of 1.


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PostPosted: Mon May 02, 2016 8:38 am 
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Joined: Fri Mar 18, 2016 3:59 am
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@tepples

Ahhh, i think i understand your confusion now. My Panel accepts 60 Hz framerate and
my fpga surly outputs at 60 Hz. I simply took the wrong number.


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PostPosted: Mon May 02, 2016 9:01 am 
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Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19341
Location: NE Indiana, USA (NTSC)
How to preserve aspect ratio when scaling to 640x480:
  • NTSC on 4:3 TV: Pad to 280 pixels wide, double, then stretch to 640
  • NTSC on 16:9 TV: Pad to 280 pixels wide, double, then squash to 480
  • PAL on 4:3 TV: Crop to 232 pixels wide, double, then stretch to 640
  • PAL on 16:9 TV: Pad to 308 pixels wide, double, then stretch to 640


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