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MMC3 IRQ disable ($E000-$FFFE, even)
http://forums.nesdev.com/viewtopic.php?f=3&t=14463
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Author:  colinvella [ Wed Jun 29, 2016 3:13 am ]
Post subject:  MMC3 IRQ disable ($E000-$FFFE, even)

My IRQ counter code for MMC3 seems to be working well. For instance, the screen splits nicely in Super Mario 3 to allow for the game stats HUD at the bottom to be rendered independently of the scrolling level. I have not encountered any issues per se (I've yet to test MMC3 extensively on this), but I do have a question concerning the phrase "acknowledge any pending interrupts" as in the case of the IRQ disable register in MMC3

Code:
IRQ disable ($E000-$FFFE, even)
7  bit  0
---- ----
xxxx xxxx
Writing any value to this register will disable MMC3 interrupts AND acknowledge any pending interrupts.


What does "acknowledge any pending interrupts" really mean? Should the MMC3 signal the CPU to do the interrupt at this point?

Thanks

Author:  Dwedit [ Wed Jun 29, 2016 3:15 am ]
Post subject:  Re: MMC3 IRQ disable ($E000-$FFFE, even)

Acknowledge means that it TURNS OFF the IRQ pin. Otherwise it would keep triggering interrupts over and over again.

Author:  Quietust [ Wed Jun 29, 2016 4:43 am ]
Post subject:  Re: MMC3 IRQ disable ($E000-$FFFE, even)

Dwedit wrote:
Acknowledge means that it TURNS OFF the IRQ pin. Otherwise it would keep triggering interrupts over and over again.

To clarify, the IRQ signal is level-sensitive (compared to NMI, which is edge-triggered) - once the timer expires, the IRQ signal is activated, and the CPU will jump to the IRQ handler at every possible opportunity (i.e. whenever the "I" flag is clear). To prevent the CPU from getting stuck in a loop rerunning the IRQ handler over and over, it needs to tell the hardware that generated the interrupt that it's done handling it and that it can deactivate the signal, and for the MMC3 this involves writing any value to $E000.

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