Buffering data bus
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Author:  Feuerwerk42 [ Mon Jul 18, 2016 8:28 am ]
Post subject:  Buffering data bus

Hi everybody

My logic level converter board is complete and im able to connect a gamepak with my FPGAnes.
Currently im figuring out how to control the address and data buses to get the rom data into my CPU.
I observed that the CPU databus only has a value while /ROMSEL is low (and CPU_RW is high of course)
, whereas i'm used to have a value read from memory for the whole duration of the next cycle inside of
my FPGA. I don't think this is a problem to me, just adding a flip flop which updates permanently with
the databus value while /ROMSEL is low but i wonder how the real CPU (and PPU) is doing this job.
Has the CPU/PPU something similar or do i simply miss something?


Author:  tepples [ Mon Jul 18, 2016 9:45 am ]
Post subject:  Re: Buffering data bus

Hold time is the time during which a digital circuit's inputs need to remain stable on the bus for the circuit to recognize them properly. Normally, you want to make hold time short to make life easier for the designers of the rest of the circuit. This requires latching the value from the data bus just as M2 is about to fall.

For the sort of hold time expected of memories connected to a 6502 processor, see the MOS 6502 datasheet.

Author:  Feuerwerk42 [ Sun Jul 24, 2016 2:05 am ]
Post subject:  Re: Buffering data bus


Ok, than my approch is quite identical. But latching the Data on the falling edge of M2?
The requested ROM-data is only available during M2 is low.


Author:  lidnariq [ Sun Jul 24, 2016 11:40 am ]
Post subject:  Re: Buffering data bus

It's a transparent latch, latching continuously while M2 is high.
This seems equivalent to a register latching on M2's falling edge, though.

Author:  Feuerwerk42 [ Sun Jul 24, 2016 12:12 pm ]
Post subject:  Re: Buffering data bus

Damn, /ROMSEL is M2 nand A15, so yes, on falling edge of M2. I mixed it up :-/

@lidnariq yes, thats the way i have to do it

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