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Rendering pipeline and the NMI_sync test
http://forums.nesdev.com/viewtopic.php?f=3&t=14823
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Author:  Alyosha_TAS [ Tue Sep 13, 2016 5:13 am ]
Post subject:  Rendering pipeline and the NMI_sync test

Hi all,

I am trying to pass the NMI_Sync test, but the middle line is 2 pixels too short. At this point I can pass every other blargg test out there, so there really isn't anything in the NMI / VBL timing I can change to try to make this test work.

I came across http://wiki.nesdev.com/w/index.php/PPU_rendering and specifically this: Actual pixel output is delayed further due to internal render pipelining, and the first pixel is output during cycle 4.

I can't find any more details about the rendering pipeline though. If I delay the EMU's pixel output by 2 ppu clocks and do the $2001 greyscale check that the test is doing there, then the test passes as expected, but I'm not sure if this is a correct implementation.

So, is there any documentation about where different checks are made in the rendering pipeline? Does anyone know if my implementation is accurate?

Thanks!

Author:  Zepper [ Tue Sep 13, 2016 2:16 pm ]
Post subject:  Re: Rendering pipeline and the NMI_sync test

In my emulator, the middle line differs in length. It flashes 3 pixels longer up to the correct size. No clues.

Author:  Eugene.S [ Thu Sep 15, 2016 6:50 am ]
Post subject:  Re: Rendering pipeline and the NMI_sync test

I've got original FC AV HVC-101 with Everdrive N8, with pinnacle capture device,
so here is test on hardware:
http://tasvideos.org/forum/viewtopic.ph ... 217#440217

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