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 Post subject: Why VBLANK is not set?!
PostPosted: Sat Oct 01, 2016 9:46 pm 
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Hello people!

Can you help to understand it:

8378 AD 02 20 LDA $2002 = FF A:10 X:00 Y:F0 P:25 SP:FA CYC:326 SL:240
837B 10 FB BPL $8378 A:10 X:00 Y:F0 P:25 SP:FA CYC:338 SL:240
8035 48 PHA A:10 X:00 Y:F0 P:25 SP:F7 CYC: 27 SL:241
8036 98 TYA A:10 X:00 Y:F0 P:25 SP:F6 CYC: 36 SL:241
8037 48 PHA A:F0 X:00 Y:F0 P:A5 SP:F6 CYC: 42 SL:241
8038 8A TXA A:F0 X:00 Y:F0 P:A5 SP:F5 CYC: 51 SL:241
8039 48 PHA A:00 X:00 Y:F0 P:27 SP:F5 CYC: 57 SL:241
803A A9 01 LDA #$01 A:00 X:00 Y:F0 P:27 SP:F4 CYC: 66 SL:241

After 837B a NMI happens; okay; But I can't understand why the VBLANK in PPU STATUS register is not 1. I expected that cpu.A: 0x90 while it's: 0x10 in instruction 8035.

Thank you! :)


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PostPosted: Sat Oct 01, 2016 9:49 pm 
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Reading from $2002 automatically clears the vblank bit.


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PostPosted: Sat Oct 01, 2016 10:01 pm 
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Yes, but why the same thing don't happens here:

8352 AD 02 20 LDA $2002 = FF A:1E X:80 Y:00 P:25 SP:FA CYC:324 SL:240
8355 10 FB BPL $8352 A:1E X:80 Y:00 P:25 SP:FA CYC:336 SL:240
8352 AD 02 20 LDA $2002 = FF A:1E X:80 Y:00 P:25 SP:FA CYC: 4 SL:241
8035 48 PHA A:9E X:80 Y:00 P:A5 SP:F7 CYC: 37 SL:241
8036 98 TYA A:9E X:80 Y:00 P:A5 SP:F6 CYC: 46 SL:241
8037 48 PHA A:00 X:80 Y:00 P:27 SP:F6 CYC: 52 SL:241
8038 8A TXA A:00 X:80 Y:00 P:27 SP:F5 CYC: 61 SL:241
8039 48 PHA A:80 X:80 Y:00 P:A5 SP:F5 CYC: 67 SL:241

?


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PostPosted: Sun Oct 02, 2016 12:00 am 
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https://wiki.nesdev.com/w/index.php/PPU ... 9_.3C_read

Focus on bit V (bit 7 / 8th bit); read the entire description, then note what SL (scanline) is when the LDA runs in 2nd code example.

Further reading: https://wiki.nesdev.com/w/index.php/PPU ... 241-260.29


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PostPosted: Sun Oct 02, 2016 6:28 am 
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NMI and the VBLANK status flag become active/inactive at the same time.
NMI can only happen at the beginning of an instruction, but LDA instructions don't perform the read until the end of the instruction.
Thus, in a "label: LDA $2002 ; BPL label" loop, there are 3 possible outcomes:

1. NMI happens during the LDA instruction, causing the accumulator to have bit 7 set; the next read from $2002 will have bit 7 clear.
2. NMI happens during the BPL instruction, causing the accumulator to have bit 7 clear; the next read from $2002 will have bit 7 set (unless you wait past the end of VBLANK).
3. NMI happens exactly at the end of the LDA instruction, causing the accumulator to have bit 7 clear and the next read from $2002 to also have bit 7 clear.

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PostPosted: Sun Oct 02, 2016 1:02 pm 
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Ow, now I understand how it worls.

Thank you!


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