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PostPosted: Sat Dec 16, 2017 3:35 pm 
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Posts: 504
Here is my preliminary analysis.
Edit 1: Updated with krzysiobal's comment.
Edit 2: Updated with krzysiobal's final pinout, and analysis based on that.
Code:
NTDEC8701                       AX-24G
---------                       ------
Pin#    Meaning                 Pin#    Meaning
1       PRG-A13                 1       ?
2       PRG-A14                 2       ?
3       PRG-A16                 3       ?
4       PRG-A15                 4       ?
5       CHR-A14                 5       to 15
6       CHR-A11                 6       PRG-A15
7       CHR-A13                 7       CHR-A14
8       CHR-A12                 8       CHR-A13
9       CPU-D2                  9       CPU-D0
10      CPU-D3                  10      CPU-D1
11      CPU-D1                  11      CPU-D2
12      GND                     12      GND
13      CHR-A15                 13      to 16
14      CHR-A10                 14      ?
15      PPU-A10                 15      to 5
16      PPU-A11                 16      to 13
17      PPU-A12                 17      Vcc
18      CPU-D4                  18      CPU-D3
19      CPU-D5                  19      CPU-D4
20      CPU-D0                  20      CPU-D5
21      CPU-R/W                 21      CPU-R/W
22      M2                      22      M2
23      PRG-!OE                 23      PRG-!OE
24      CPU-ROMSEL              24      CPU-ROMSEL
25      Vcc                     25      ?
26      CPU-A0                  26      CPU-A0
27      CPU-A13                 27      CPU-A13
28      CPU-A14                 28      CPU-A14
The IC pinouts are similar enough to conclude that the IC is the same, just connected differently. Let's start with CPU D0-D5:
Code:
Jovial Race     Normal
-----------     ------
D5              D0             
D2              D1             
D0              D2             
D1              D3             
D3              D4             
D4              D5             
Jovial Race writes $01,$04,$21,$24 to $8000. The NTDEC8701 thus sees the following register numbers:
Code:
Jovial Race     Normal
-----------     ------
$01             $04
$04             $02
$21             $05
$24             $03
So, Jovial Race only initializes the bank registers for PPU $1000-$1FFF, at least if PPU A12 were connected normally, and no PRG register. To make these bank registers affect the entire 8 KiB CHR-ROM range and not just $1000-$1FFF, Jovial Race connects the AX-24's PPU-A12 line (pin 17) to Vcc so that it is permanently "1". What about the bank register values? Jovial Race writes:
Code:
$10     for 8 KiB CHR-ROM bank 0
$01     for 8 KiB CHR-ROM bank 1
$1A     for 8 KiB CHR-ROM bank 2
$0B     for 8 KiB CHR-ROM bank 3
OR'd with $04 to choose 32 KiB PRG-ROM bank 1.
Which means that for the bank data that Jovial Race writes, the NTDEC8701 sees the following data:
Code:
Jovial Race     Normal
-----------     ------
$10             $20     for 8 KiB CHR-ROM bank 0
$01             $04     for 8 KiB CHR-ROM bank 1
$1A             $38     for 8 KiB CHR-ROM bank 2
$0B             $1C     for 8 KiB CHR-ROM bank 3
OR'd with:
$04             $02     and for 32 KiB PRG-ROM bank 1
Now, on the Namco 108/NTDEC8701, the several CHR bank register bits (as the Namco 108 sees them) become the following CHR address bits:
Code:
$02             Normally CHR A11, pin 6, which is PRG A15 on Jovial Race.
$04             Normally CHR A12, pin 8, which is CHR A13 on Jovial Race.
$08             Normally CHR A13, pin 7, which is CHR A14 on Jovial Race.
$10             Normally CHR A14, pin 5, which Jovial Race connects to PPU-A10 (pin 15).
$20             Normally CHR A15, pin 13, which Jovial Race connects to PPU-A11 (pin 16).
As for the last two lines of the previous table, Jovial Race's use of bits 3 and 4 (bits 4 and 5 from the IC's perspective) force the IC to think that any CHR-ROM access falls into the same 1 KiB region that is determined by the highest two bits of the bank register value (which ultimately become PPU-A10 and PPU-A11) and the permanently-high PPU-A12:
Code:
8 KiB
CHR-ROM $8001   IC      CHR
bank    bits    bits    range
------- -----   -----   -----
0       $10     $20     $1800-$1BFF
1       $00     $00     $1000-$13FF
2       $18     $30     $1C00-$1FFF
3       $08     $10     $1400-$17FF

(only bits relevant for the CHR range shown)
If the four relevant bank registers are initialized to the same value, then the two highest bank register value bits become irrelevant (which is why our dumping script variant that leaves them at zero still works). If they are not all set to the same value however, then interesting things might occur, as writing to one bank register also changes which bank register is the relevant one. At this point, I think that this must be a copy-protection measure.

To summarize: Everything checks out that Jovial Race's AX-24G is a Namco-108-compatible NTDEC8701 connected to function like a simple GNROM-like latch. The reason for doing so must have been either that Joy Van had a surplus of these chips lying around in those early days, or as a (rather ineffective) copy-protection measure.

Thanks two million, krzysiobal and sdm! Comments and corrections welcome. :)


Last edited by NewRisingSun on Sun Dec 17, 2017 11:42 am, edited 5 times in total.

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PostPosted: Sat Dec 16, 2017 3:51 pm 
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ok, after some talk with SDM:
pin4=PRG-A15, pin6=CHR A11


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PostPosted: Sun Dec 17, 2017 4:42 am 
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Joined: Tue Apr 11, 2006 4:08 am
Posts: 262
It's hard to check without removing the roms. I used a strong, spotlight LED to see the path shadows.

NTDEC #15 = Famicom Conn. #53
NTDEC #16 = Famicom Conn. #54
NTDEC #03 = 74hc139 #02 (PRG A16? - because they are 2x PRG 27C512 MaskROM)
NTDEC #08 = hard to track, it goes under CHR ROM.
NTDEC #13 = (see picture, #13 to SW Select 5V (CHR 32KB or smaller)<->CHR A15(CHR 64KB+) ?? or... as an option to control mirroring when CHR RAM is used?? (second switch - CIRAM A10 to NTDEC #13 (CRAM)<->CHR A10 (CROM))

Interesting, because the 206 mapper does not have support for CHR RAM. The possible PCB was also designed for a different mapper with CHR RAM (Maybe some simplified MMC3 clone?? Or NTDEC8701 has support for CHR RAM..).


Attachments:
NTDECpin13.jpg
NTDECpin13.jpg [ 362.41 KiB | Viewed 752 times ]
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PostPosted: Sun Dec 17, 2017 6:49 am 
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Posts: 504
That leaves no pin for PPU-A12 (Famicom Conn. #55). One of these must be PPU-A12.


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PostPosted: Sun Dec 17, 2017 9:01 am 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 316
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Ok, I am almost sure that this is the final pinout:
Code:
PRG-A13  1  28 CPU-A14
PRG-A14  2  27 CPU-A13
PRG-A16  3  26 CPU-A0
PRG-A15  4  25 VCC
CHR-A14  5  24 CPU-!ROMSEL
CHR-A11  6  23 PRG-!OE
CHR-A13  7  22 M2
CHR-A12  8  21 CPU-R/!W
CPU-D2   9  20 CPU-D0
CPU-D3  10  19 CPU-D5
CPU-D1  11  18 CPU-D4
GND     12  17 PPU-A12
CHR-A15 13  16 PPU-A11
CHR-A10 14  15 PPU-A10


Image Image

Last thing that does not match is this connection - this solder jumper selects mirroring, but there is no way for these 2 connections to exist and i have no idea how they could route it any other way:

Really no chance to take multimeter and check for continuity?

Quote:
NTDEC #13 = (see picture, #13 to SW Select 5V (CHR 32KB or smaller)<->CHR A15(CHR 64KB+) ?? or... as an option to control mirroring when CHR RAM is used?? (second switch - CIRAM A10 to NTDEC #13 (CRAM)<->CHR A10 (CROM))

NTDEC #13 = CHR-A15. This solder switch at bottom layer just selects what is CHR.PIN1 driven with - CHR-A15 or
+5V (for CHR-ROM smaller than 64 KB, PIN1 is VPP and it should be tied to VCC)

This mapper does not support mirroring select and mirroring is hardwired with the solder jumper at top layer.

Quote:
Interesting, because the 206 mapper does not have support for CHR RAM. The possible PCB was also designed for a different mapper with CHR RAM (Maybe some simplified MMC3 clone?? Or NTDEC8701 has support for CHR RAM..)

CHR-RAM or CHR-ROM is not a matter of mapper support. Any mapper can be used with CHR-RAM or CHR-ROM, just place CHR-RAM in place of CHR-ROM. However, this PCB was not designed for CHR-RAM because PPU_!WR at pin header is not routed to anything.


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PostPosted: Sun Dec 17, 2017 10:40 am 
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Thanks again, everyone! I have updated my post with the final analysis, in which no more unresolved points remain. :)

For what it's worth, attached find a Nintendulator source file (edit: slight simplifcation update) that implements the board's functionality as described. Again, since that early release of Jovial Race also has the $4120 compatibility write, there is no reason to actually include this in an emulator. I wrote it to verify that the described logic yields a working emulation, and it does. (Should any undumped Sachen cart turn up that also uses this board type, and the game does not have a $4120 compatibility write, then this source file will become relevant for emulator authors.)


Attachments:
mapper133alt.cpp [1.23 KiB]
Downloaded 25 times


Last edited by NewRisingSun on Sun Dec 17, 2017 4:07 pm, edited 2 times in total.
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PostPosted: Sun Dec 17, 2017 12:42 pm 
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krzysiobal wrote:
CHR-RAM or CHR-ROM is not a matter of mapper support. Any mapper can be used with CHR-RAM or CHR-ROM, just place CHR-RAM in place of CHR-ROM. However, this PCB was not designed for CHR-RAM because PPU_!WR at pin header is not routed to anything.


I was talking about controlling the mirroring by the mapper chip.

I wonder why is this switch / jumper (CIRAM A10->#13/CHR A10) here if it does not use CHR RAM?


Attachments:
PICT0015.JPG
PICT0015.JPG [ 712.63 KiB | Viewed 686 times ]
PICT0016.JPG
PICT0016.JPG [ 723.75 KiB | Viewed 686 times ]
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PostPosted: Sun Dec 17, 2017 1:51 pm 
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Thanks for photo without chips.
This jumper selects betwen Vertical/Single Screen mirroring (this cartridge is hardwired to Vertical, but in case of single screen mirroring, CHR-A15 bit could be used to control screen mirroring (0/1).

Because PPU A13 is not connected to this chip, it cannot distinguish between access to pattern table ($0000-$1fff) and nametable ($2000-2fff), so CHR-A15 (upper CHR bit):
* set for bank $0000-$07ff will also set nametable at $2000 and $2400
* set for bank $0800-$0fff will also set nametable at $2800 and $2c00


Last edited by krzysiobal on Sun Dec 17, 2017 2:02 pm, edited 1 time in total.

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PostPosted: Sun Dec 17, 2017 1:54 pm 
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sdm wrote:
I wonder why is this switch / jumper (CIRAM A10->#13/CHR A10) here if it does not use CHR RAM?
krzysiobal wrote:
This jumper selects betwen Vertical/Single Screen mirroring (this cartridge is hardwired to Vertical, but in case of single screen mirroring, CHR-A15 bit could be used to control screen mirroring (0/1).
So it's for making pirate copies of mapper 95's Dragon Buster...


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PostPosted: Mon Dec 18, 2017 2:09 am 
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nesdev wiki wrote:
If this feedback path doesn't settle on one specific register, then the selected banks will rapidly switch between all the registers specified by the feedback path, and the 108 clone will get hot.
I wonder how this relates to the delay that we had to add to the dumping script after setting up the four registers.


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PostPosted: Mon Dec 18, 2017 6:21 am 
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Isn't the delay caused by the PRG-A15 transistor inverting circuit, which needs time to went out of saturation state?
There is even no capacitor in series with base resistor that could speed that up.


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PostPosted: Mon Dec 18, 2017 11:01 am 
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NewRisingSun wrote:
I wonder how this relates to the delay that we had to add to the dumping script after setting up the four registers.
You always wrote the same value (0) into those two bits in all four registers, so that shouldn't be relevant.


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