|Correct emulation of PAL DMC DMA cycle steals
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|Author:||Bananmos [ Sun Mar 11, 2018 4:41 am ]|
|Post subject:||Correct emulation of PAL DMC DMA cycle steals|
Whilst trying out the new nifty PPU write register debug view in the Mesen emulator, I've realised that we still don't have correct emulation for the cycles stolen by the DMC DMA for PAL NES systems.
I tried running my old "Years Behind" music demo from 2003: https://files.scene.org/view/parties/2003/mainframe03/demo_8bit/retrocoders_-_years_behind.zip
This demo runs on PAL systems only, and compensates for the DMA DMC cycle steal by adjusting the skipped/taken cycle every scanline based on the current DMC playback rate. It's not 100% perfect, but mostly comes pretty close at keeping the writes within the safe hblank window.
(keep in mind some of the PPU register writes do happen before the hblank. This is perfectly fine, because they only affect the temporary 't' register rather than the 'v' register)
I've hacked this demo to replace the scroll register writes with writes to $2001 which enable/disable monochrome mode.
The hacked version can be found here: https://drive.google.com/open?id=1Uxsdx6t6Y4xjdIMyRzEDelK4vlOplhYZ
And a video of it running on my PAL NES is here: https://drive.google.com/open?id=1JVvSYFIShNs_zHKjv7CJBRKsBdD9SCcr
Running the demo in an emulator produces a noticeably different view compared to the video, as the purple bar gets skewed *a lot more* and wraps around to the left side of the screen. Here's a screenshot in Mesen, for example:
I've also tried Nintendulator and FCEUX, and the results look pretty consistent with Mesen. So it looks like there's still an unsolved mystery when it comes to DMC DMA behavior on PAL systems.
Getting this right will probably involve a lot of analysis and test ROM writing. I don't have the time/motivation to be in the driving seat for this one, so just putting it out there in case someone is looking for one last emulation mystery to unravel.
But I'd be happy to assist with testing on my PAL console if anyone else picks this up.
Good starting points could be the DMC DMA tests previously done for NTSC systems:
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