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 Post subject: Sprite rendering?
PostPosted: Fri May 04, 2018 6:28 pm 
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I'm rewritting my PPU rendering engine to match the hardware procedure, so my question might sound silly...

The wiki says... (PPU) Cycles 257-320 - the tile data for the sprites on the next scanline are fetched here. Again, each memory access takes 2 PPU cycles to complete, and 4 are performed for each of the 8 sprites:
257 Garbage nametable byte
258 Garbage nametable byte
259 Tile bitmap low
260 Tile bitmap high (+8 bytes from tile bitmap low)


At same time, there's the sprite evaluation. Wiki says... Cycles 257-320: Sprite fetches (8 sprites total, 8 cycles per sprite)

1-4: Read the Y-coordinate(257), tile number(258), attributes(259), and X-coordinate(260) of the selected sprite from secondary OAM
5-8: Read the X-coordinate of the selected sprite from secondary OAM 4 times (while the PPU fetches the sprite tile data)
For the first empty sprite slot, this will consist of sprite #63's Y-coordinate followed by 3 $FF bytes; for subsequent empty sprite slots, this will be four $FF bytes


Well, how is this done at same time??? Could someone clarify it?


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 Post subject: Re: Sprite rendering?
PostPosted: Fri May 04, 2018 6:49 pm 
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The pages to which you refer are PPU rendering and PPU sprite evaluation.

The PPU can access OAM and VRAM at once. It does so, for example, when clearing secondary OAM at x=1-64 and when searching for sprites in range at x=65-240. Its cycle by cycle action in the first of eight sprite sequences in x=257-320 is as follows:

257 (VRAM): Send address of garbage nametable byte to latch
257 (OAM): Read Y

258 (VRAM): Read garbage nametable byte
258 (OAM): Read tile number

259 (VRAM): Send address of garbage nametable byte to latch
259 (OAM): Read attributes

260 (VRAM): Read garbage nametable byte
260 (OAM): Read X coordinate

261 (VRAM): Send address of sprite sliver bitplane 0 to latch, based on OAM reads at 257 and 258
261 (OAM): Reread X coordinate

262 (VRAM): Read sprite sliver bitplane 0
262 (OAM): Reread X coordinate

263 (VRAM): Send address of sprite sliver bitplane 1 to latch, based on OAM reads at 257 and 258
263 (OAM): Reread X coordinate

264 (VRAM): Read sprite sliver bitplane 1
264 (OAM): Reread X coordinate


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 Post subject: Re: Sprite rendering?
PostPosted: Fri May 04, 2018 7:12 pm 
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What? It says "the tile data for the sprites on the next scanline are fetched here". Since the sprites don't use nametable bytes, there are garbage bytes. So, at PPU cycle:

257 and 258 - two garbage nametable bytes;
259 - tile bitmap low, which fetches CHR data from PPU $0000-$1FFF;
260 - tile bitmap high.

With this, sprite 0 CHR data fetching is done.
Your diagram doesn't match this. What part am I misunderstanding now???


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 Post subject: Re: Sprite rendering?
PostPosted: Fri May 04, 2018 9:17 pm 
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Where on that page do the numbers 259 and 260 appear in that context?

It does not say:

257. Garbage nametable byte
258. Garbage nametable byte
259. Tile bitmap low
260. Tile bitmap high (+8 bytes from tile bitmap low)


Instead, it says:

Again, each memory access takes 2 PPU cycles to complete, and 4 are performed for each of the 8 sprites:

1. Garbage nametable byte
2. Garbage nametable byte
3. Tile bitmap low
4. Tile bitmap high (+8 bytes from tile bitmap low)


I understand "each memory access takes 2 PPU cycles to complete" to mean the following:

257. Garbage nametable byte
259. Garbage nametable byte
261. Tile bitmap low
263. Tile bitmap high (+8 bytes from tile bitmap low)


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 Post subject: Re: Sprite rendering?
PostPosted: Sat May 05, 2018 6:38 am 
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Well, the MMC3 IRQ is clocked at PPU cycle 259 (the 260th), exactly the sprite tile fetching from VRAM. The 2nd sprite byte is the tile number, fetched from PPU cycle 258 (the 259th).
Strange... because 257 + 2 cycles x 4 access x 8 sprites = 321.


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