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 Post subject: Taito TC0690 IRQs
PostPosted: Mon Jan 07, 2019 10:48 am 
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Splitting from a discussion that came up in another unrelated thread ...

Mapper 48's IRQ is stated as being generated later than on the MMC3, but there is more: It seems impossible to get the IRQs to fire at the correct scanline in both The Jetsons: Cogswell's Caper's title screen and The Flintstones: The Rescue of Dino&Hoppy's status bar, either one will be off by one. The wiki page advises to XOR the latch value with FF to get the MMC3 equivalent value, which indicates that Taito's chip counts up, not down. When counting up, there is always the question of raising the IRQ when the counter reaches $FF (similar to the Namco 163's CPU Cycle counter) or when it wraps from $FF to $00. I noticed that Flintstones works well when raising the IRQ at counter $FF, while Jetsons works well when raising the IRQ at the time that the counter wraps (plus a delay of at least six CPU cycles, not four as the wiki states). This may be a coincidence, but it is the sort of thing that one would expect from a chip revision. If this hypothesis could be tested with the chips found in cartridges of both games, and confirmed, then a submapper could be allocated to indicate the IRQ counter behavior.


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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Mon Jan 07, 2019 2:23 pm 
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The only direct evidence we have so far is the picture Overload took of "The Flintstones: The Rescue of Dino & Hoppy"-
Attachment:
File comment: source: talk page for mapper 33
taito-tc0690fmi-mw22745.jpg
taito-tc0690fmi-mw22745.jpg [ 10.29 KiB | Viewed 4152 times ]


On this board ("J9100300A") there is also a 74LS157 wired up to serve as a transparent latch, where it holds copies of PPU A12 and PPU A13 ... I can't see all the signals but I think it's transparent while PPU/RD is high ... and these latched copies then go to the TC0690.

Given my understanding of how the PPU fetch cadence works, I don't see how that would change anything.


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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Mon Jan 07, 2019 5:54 pm 
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That reads like a circuit to prevent clocking the scanline counter when writing to $2006 mid-frame. Unfortunately, neither Flintstones not Jetsons do that (Flintstones at least not pre-IRQ), so it is unrelated.


Last edited by NewRisingSun on Mon Jan 07, 2019 6:01 pm, edited 1 time in total.

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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Mon Jan 07, 2019 6:00 pm 
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Shouldn't that be the other way? It only holds the value (and rejects new ones) when PPU/RD is low. (I mean, assuming I'm guessing connectivity correctly)


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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Mon Jan 07, 2019 6:05 pm 
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If the passed-on value is the latched one during one state of PPU /RD and transparent during the other, either A12/A13 changes are not passed on to the chip during reads or during writes. Certainly, it will not be that only write-cycle A12/A13 are fed to the scanline counter, because that would render it inoperational.


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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Mon Jan 07, 2019 7:56 pm 
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Right, but I interpreted what you were saying to mean that it was there to keep raster effects (mid-render writes to $2006) from incorrectly clocking the counter...

If my assumption about the connectivity is correct, namely it only passes through values when it's not fetching from the PPU's bus, then any random $2006 writes would pass through and clock the counter unhelpfully.

If I'm misreading it, and it's only transparent during PPU reads, then yes that would keep writes to $2006 during blanking from incorrectly clocking the counter...


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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Tue Jan 08, 2019 11:23 pm 
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A source whom I have no reason to doubt indicates that Famicom Jetsons does not show glitches on the title screen : https://www.famicomworld.com/forum/inde ... #msg183044 So I guess that it's behavior is a variant compared to Flintstones.

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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Wed Jan 09, 2019 1:34 pm 
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lidnariq wrote:
If my assumption about the connectivity is correct, namely it only passes through values when it's not fetching from the PPU's bus
I am unsuccessfully trying to wrap my head around what exactly it means when you are only passing through values when the PPU is NOT reading, and what the purpose of such a thing would be. Unless the game is writing, won't the address that is then passed on just be what the PPU was reading from earlier? So is it basically just a delay?


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 Post subject: Re: Taito TC0690 IRQs
PostPosted: Wed Jan 09, 2019 2:01 pm 
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NewRisingSun wrote:
and what the purpose of such a thing would be.
That is exactly where I'm getting stuck also.
Quote:
Unless the game is writing,
Writing vs not isn't relevant here... PPU /WR definitely does not proceed from the card edge.

Quote:
So is it basically just a delay?
I'm not even convinced it's a delay? Beyond the standard 74LS TTL propagation delay, anyway. Which may have been accidentally enough for whatever they needed.

The only signals in the area at all are PPU/RD, CIRAM A10, and CHR banking outputs A12, A15, A16.


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